Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12439593-B2
Application number	US-202217685835-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Jun 22, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor memory device includes a substrate, a plurality of first conductive layers and a plurality of first insulating layers alternately arranged in a first direction intersecting the substrate, a first semiconductor layer extending in the first direction and facing the first semiconductor layers and the first insulating layers, a first charge storage layer disposed between the first conductive layers and the first semiconductor layer, and a second semiconductor layer connected to one end of the first semiconductor layer in the first direction. The first insulating layers at least partially contains a first element. The first element is at least one of phosphorus (P), arsenic (As), carbon (C), and argon (Ar).

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers and a plurality of first insulating layers alternately arranged in a first direction, the first direction intersecting the substrate;
a first semiconductor layer extending in the first direction, the first semiconductor layer facing the first conductive layers and the first insulating layers;
a charge storage layer disposed between the first conductive layers and the first semiconductor layer; and
a second semiconductor layer connected to one end of the first semiconductor layer in the first direction, wherein
the second semiconductor layer contains a first element,
the first element is at least one of phosphorus (P), arsenic (As), carbon (C), or argon (Ar),
the second semiconductor layer including:
a fourth region,
a fifth region disposed between the fourth region and the charge storage layer,
a sixth region disposed above the fourth region,
a seventh region disposed between the sixth region and the charge storage layer, and
an eighth region disposed between the fifth region and the seventh region, and directly contacting the first semiconductor layer,

wherein a concentration of the first element in the fifth region is larger than a concentration of the first element in the fourth region, and a concentration of the first element in seventh region is larger than a concentration of the first element in the sixth region and fourth region.

2. The semiconductor memory device according to claim 1 , wherein the first element is carbon (C), comprising:
a ninth region disposed below the eighth region, and
a tenth region disposed above the eighth region,
wherein a concentration of carbon (C) in the ninth region is larger than a concentration of carbon in the sixth region and the fourth region, and a concentration of carbon in the tenth region is larger than a concentration of carbon in the sixth region and the fourth region.

3. The semiconductor memory device according to claim 1 , wherein the first conductive layers include a stacked film.

4. The semiconductor memory device according to claim 3 , wherein the stacked film includes a barrier conductive film.

5. The semiconductor memory device according to claim 4 , wherein the stacked film includes a metal film.

6. The semiconductor memory device according to claim 3 , wherein the stacked film includes a doped polycrystalline silicon film.

7. The semiconductor memory device according to claim 1 , wherein the first insulating layers include silicon oxide.

8. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is at least one of a memory die, a memory system including a controller die, a memory card, or a solid state drive (SSD).

9. The semiconductor memory device according to claim 1 , wherein the first semiconductor layer includes polycrystalline silicon.

10. The semiconductor memory device according to claim 1 , wherein the first semiconductor layer is substantially cylindrical in shape.

11. The semiconductor memory device according to claim 1 , wherein the first charge storage layer is substantially cylindrical in shape.

12. The semiconductor memory device according to claim 1 , wherein the first charge storage layer includes polycrystalline silicon.

Assignees

• Kioxia Corp

Inventors

• Sato Hiroyasu

Classifications

• H10B43/00

  EEPROM devices comprising charge-trapping gate insulators · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/00

  Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title