Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12439585-B2
Application number	US-202217843921-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Aug 3, 2020
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A method of manufacturing a semiconductor device comprises: forming a first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor being located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; forming a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; and forming a second capacitor located at a second part of the first intersection.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor being located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line;
forming a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; and
forming a second capacitor located at a second part of the first intersection,
wherein forming of the first capacitor and forming of the second capacitor include:
forming first electrode layers of the first and second capacitors extending in a vertical direction and overlapping with the first intersection in the vertical direction;
forming a dielectric layer surrounding each of sidewalls of the first electrode layers; and
forming a second electrode layer surrounding the sidewall of the first electrode layer of the first capacitor and continuously extending to surround the sidewall of the first electrode layer of the second capacitor, wherein the dielectric layer is disposed between the second electrode and each of the first electrode layers.

2. The method of claim 1 , wherein the forming of the first array includes:
forming the first bit line and first channel layers located on the first bit line;
forming a first gate insulating layer surrounding the first channel layers; and
forming the first word line, surrounding the first channel layers, on the first gate insulating layer.

3. The method of claim 1 , further comprising forming a second contact structure connected to the second capacitor.

4. The method of claim 1 , further comprising forming a array above the first capacitor and the second capacitor, wherein the second array includes a second bit line, a second word line intersecting the second bit line, and a second transistor located at a second intersection of the second word line and the second bit line, the second transistor being connected between the second word line and the second bit line.

5. The method of claim 4 , wherein the forming of the second array includes:
forming a second channel layer connected to the second capacitor;
forming a second gate insulating layer surrounding the second channel layer;
forming the second word line, surrounding a sidewall of the second channel layer, on the second gate insulating layer; and
forming the second bit line connected to the second channel layer on the second word line.

6. A method of manufacturing a semiconductor device, the method comprising:
forming a first array including a first bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction, and a first transistor being located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line;
forming a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; and
forming a second capacitor located at a second part of the first intersection,
wherein the forming of the first capacitor includes:
forming a first sacrificial layer on the first array;
forming a cap layer on the first sacrificial layer;
forming a second sacrificial layer on the cap layer; and
forming a first opening penetrating the second sacrificial layer, the cap layer, and the first sacrificial layer.

7. The method of claim 6 , further comprising:
forming a second opening connected to the first opening, the second opening exposing a first channel layer of the first transistor; and
forming a first contact structure connected to the first channel layer in the second opening.

8. The method of claim 6 , wherein the forming of the first capacitor further includes:
forming a first electrode layer in the first opening;
forming a second opening by removing the first sacrificial layer;
forming a third opening by removing the second sacrificial layer;
forming a first dielectric layer in the second opening;
forming a second electrode layer in the first dielectric layer;
forming a second dielectric layer in the third opening; and
forming a third electrode layer in the second dielectric layer.

9. The method of claim 8 , wherein the third opening is formed when the second opening is formed, the second dielectric layer is formed when the first dielectric layer is formed, and the third electrode layer is formed when the second electrode layer is formed.

10. The method of claim 6 , wherein the forming of the second capacitor includes:
forming a first electrode layer in the first opening;
forming a second opening by removing the first sacrificial layer;
forming a third opening by removing the second sacrificial layer;
forming a first dielectric layer in the second opening;
forming a second electrode layer in the first dielectric layer;
forming a second dielectric layer in the third opening; and
forming a third electrode layer in the second dielectric layer.

11. The method of claim 10 , wherein a bottom surface of the second opening is located between a bottom surface and a top surface of the first sacrificial layer.

Assignees

• Sk Hynix Inc

Inventors

• Han Jae Hyun

Classifications

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10B12/33 Primary

  the capacitor extending under the transistor · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10B12/01

  Manufacture or treatment · CPC title