Efficient seamless switching of sigma-delta modulators

Patent metadata

Field	Value
Publication number	US-12439204-B2
Application number	US-202318298854-A
Country	US
Kind code	B2
Filing date	Apr 11, 2023
Priority date	Aug 5, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A digital microphone includes at least one integrator; a state detection and parameter control component directly coupled to an output of the integrator; and a signal processing component coupled to an output of the state detection and parameter control component, wherein a parameter of the signal processing component includes a first value in a first operational mode and a second value in a second operational mode different from the first operational mode.

First claim

What is claimed is:

1. A digital modulator comprising:
a summer;
at least one integrator coupled to the summer;
a quantizer coupled to the at least one integrator;
a state detection and control component coupled to an output of the at least one integrator; and
a variable gain block coupled between the quantizer and the summer,
wherein a gain control output of the state detection and control component is coupled to a gain control input of the variable gain block.

2. The digital modulator of claim 1 , wherein the state detection and control component is configured for generating a first output signal if a state of the integrator is between a first threshold and a second threshold, and for generating a second output signal if the state of the integrator is not between the first threshold and the second threshold.

3. The digital modulator of claim 2 , wherein the variable gain block is configured for having a first gain value in response to the first output signal and for having a second gain value in response to the second output signal.

4. The digital modulator of claim 1 , wherein the summer is configured for receiving an “m” bit input signal, wherein “m” is an integer greater than one, and wherein the quantizer is configured for providing a single bit output signal.

5. The digital modulator of claim 1 , wherein the at least one integrator comprises a plurality of serially-coupled integrators.

6. The digital modulator of claim 1 , further comprising a loop filter interposed between the at least one integrator and the quantizer.

7. The digital modulator of claim 1 , wherein the state detection and control component is configured so that when the at least one integrator is in a zero state or between first and second thresholds, the state detection and control component generates a first signal.

8. The digital modulator of claim 7 , wherein the state detection and control component is configured so that when the at least one integrator is in a maximum positive state or a maximum negative state outside of the first and second thresholds, the state detection and control component generates a second signal.

9. A digital modulation method comprising:
summing an input signal and an output signal of a variable gain block in a summer;
coupling at least one integrator to the summer;
coupling a quantizer to the at least one integrator;
coupling a state detection and control component to an output of the at least one integrator;
coupling the variable gain block between the quantizer and the summer; and
controlling a gain control input of the variable gain block with a gain control output of the state detection and control component.

10. The method of claim 9 , wherein the state detection and control component generates a first output signal if a state of the integrator is between a first threshold and a second threshold, and generates a second output signal if the state of the integrator is not between the first threshold and the second threshold.

11. The method of claim 10 , wherein the variable gain block has a first gain value in response to the first output signal and for having a second gain value in response to the second output signal.

12. The method of claim 9 , wherein the summer receives an “m” bit input signal, wherein “m” is an integer greater than one, and wherein the quantizer provides a single bit output signal.

13. The method of claim 9 , wherein the at least one integrator comprises a plurality of serially-coupled integrators.

14. The method of claim 9 , further comprising loop filtering the at least one integrator.

15. The method of claim 9 , wherein, when the at least one integrator is in a zero state or between first and second thresholds, the state detection and control component generates a first parameter adjusting signal.

16. The method of claim 15 , wherein, when the at least one integrator is in a maximum positive state or a maximum negative state outside of the first and second thresholds, the state detection and control component generates a second parameter adjusting signal.

17. A digital modulator comprising:
at least one integrator coupled to an input of the digital modulator;
a quantizer coupled to the at least one integrator and to an output of the digital modulator;
a state detection and control component coupled to an output of the at least one integrator;
a variable gain block coupled between the input of the digital modulator and the quantizer; and
wherein a gain control output of the state detection and control component is coupled to a gain control input of the variable gain block.

18. The digital modulator of claim 17 , wherein the state detection and control component is configured for generating a first output signal if a state of the integrator is between a first threshold and a second threshold, and for generating a second output signal if the state of the integrator is not between the first threshold and the second threshold.

19. The digital modulator of claim 18 , wherein the variable gain block maintains a current gain value in response to the first output signal of the state detection and control component, and wherein the variable gain block changes the current gain value in response to the second output signal.

20. The digital modulator of claim 17 , wherein the input of the digital modulator comprises a multi-bit input, and the output of the digital modulator comprises a single bit output.

Assignees

• Infineon Technologies Ag

Inventors

• Straeussnigg Dietmar

Classifications

• H03M5/08

  Code representation by pulse width · CPC title

• H03M3/00

  Conversion of analogue values to or from differential modulation · CPC title

• H03M3/488

  using automatic control · CPC title

• H03M1/18

  Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging · CPC title

• H04R2201/003

  Mems transducers or their use · CPC title