Providing high assurance of end-to-end CPRI circuit in a high jitter packet based fronthaul network

Patent metadata

Field	Value
Publication number	US-12438830-B2
Application number	US-202217824077-A
Country	US
Kind code	B2
Filing date	May 25, 2022
Priority date	May 25, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

The present disclosure is directed to ensuring end-to-end packet delivery in a Common Public Radio Interface (CPRI) circuit with a high jitter packet-based fronthaul network. In one aspect, a method includes determining, at a de-mapper, that at least one data packet scheduled to be played out is not available; inserting an idle data packet into a buffer at the de-mapper for each data packet that is not available; continuously monitoring a packet playout process to (1) identify last valid data packet played out, (2) a number of idle data packets inserted, and (3) a number of data packets currently stored in the buffer; and determining that insertion of idle data packets into the buffer should be stopped and a valid data packet to be played out; wherein inserting the idle data packet and the valid data packet ensure link integrity in data packet transmission between two network elements.

First claim

What is claimed is:

1. A method comprising:
determining, at a de-mapper configured to receive data packets over a network, that at least one data packet scheduled to be played out is not available;
inserting an idle data packet into a buffer at the de-mapper for each of the at least one data packet that is not available, wherein a size of the idle data packet is equal to a size of a Radio over Ethernet (RoE) frame;
continuously monitoring, at the de-mapper, a packet playout process to (1) identify last valid data packet played out, (2) a number of idle data packets inserted, and (3) a number of data packets currently stored in the buffer; and
based on the continuous monitoring, determining that insertion of idle data packets into the buffer should be stopped and a valid data packet to be played out; wherein inserting the idle data packet and the valid data packet ensure link integrity in data packet transmission between two network elements in the network.

2. The method of claim 1 , wherein content of the idle data packet does not result in PCS errors on a Common Public Radio Interface (CPRI) link between the de-mapper and one of the two network elements.

3. The method of claim 1 , further comprising:
identifying the valid data packet to be played out.

4. The method of claim 3 , wherein the valid data packet is identified based on at least one of a sequence number or a timestamp associated with a corresponding ROE frame, the sequence number or the timestamp being stored in a RoE header or a mapping table.

5. The method of claim 1 , further comprising:
detecting a buffer underrun at the de-mapper.

6. The method of claim 5 , wherein upon detecting the buffer underrun, the method further comprises:
adjusting a re-timer output delay for the buffer using an average data packet delay obtained from an initial CPRI link establishment and an estimated fill time for the buffer.

7. The method of claim 1 , wherein the de-mapper is part of a fronthaul gateway that converts received Ethernet packets into CPRI packets to be played out at one of a Radio Control Equipment or a Radio Equipment.

8. A de-mapper of a fronthaul network comprising:
one or more memories having computer-readable instructions stored therein; and
one or more processors configured to execute the computer-readable instructions to:
determine that at least one data packet scheduled to be played out is not available;
insert an idle data packet into a buffer at the de-mapper for each of the at least one data packet that is not available, wherein a size of the idle data packet is equal to a size of a Radio over Ethernet (RoE) frame;
continuously monitor, at the de-mapper, a packet playout process to (1) identify last valid data packet played out, (2) a number of idle data packets inserted, and (3) a number of data packets currently stored in the buffer; and
based on the continuous monitoring, determine that insertion of idle data packets into the buffer should be stopped and a valid data packet to be played out;
wherein insert the idle data packet and the valid data packet ensure link integrity in data packet transmission between two network elements in the network.

9. The de-mapper of claim 8 , wherein content of the idle data packet does not result in PCS errors on a Common Public Radio Interface (CPRI) link between the de-mapper and one of the two network elements.

10. The de-mapper of claim 8 , wherein the one or more processors are further configured to execute the computer-readable instructions to identify the valid data packet to be played out.

11. The de-mapper of claim 10 , wherein the valid data packet is identified based on at least one of a sequence number or a timestamp associated with a corresponding ROE frame, the sequence number or the timestamp being stored in a RoE header or a mapping table.

12. The de-mapper of claim 8 , wherein the one or more processors are further configured to execute the computer-readable instructions to detect a buffer underrun at the de-mapper.

13. The de-mapper of claim 12 , wherein upon detecting the buffer underrun, the one or more processors are further configured to execute the computer-readable instructions to adjust a re-timer output delay for the buffer using an average data packet delay obtained from an initial CPRI link establishment and an estimated fill time for the buffer.

14. The de-mapper of claim 8 , wherein the de-mapper is part of a fronthaul gateway that converts received Ethernet packets into CPRI packets to be played out at one of a Radio Control Equipment or a Radio Equipment.

15. One or more non-transitory computer-readable media comprising computer-readable instructions, which when executed by one or more processors of a de-mapper in a fronthaul network, cause the de-mapper to:
determine that at least one data packet scheduled to be played out is not available;
insert an idle data packet into a buffer at the de-mapper for each of the at least one data packet that is not available, wherein a size of the idle data packet is equal to a size of a Radio over Ethernet (RoE) frame;
continuously monitor, at the de-mapper, a packet playout process to (1) identify last valid data packet played out, (2) a number of idle data packets inserted, and (3) a number of data packets currently stored in the buffer; and
based on the continuous monitoring, determine that insertion of idle data packets into the buffer should be stopped and a valid data packet to be played out; wherein insert the idle data packet and the valid data packet ensure link integrity in data packet transmission between two network elements in the network.

16. The one or more non-transitory computer-readable media of claim 15 , wherein content of the idle data packet does not result in PCS errors on a Common Public Radio Interface (CPRI) link between the de-mapper and one of the two network elements.

17. The one or more non-transitory computer-readable media of claim 15 , wherein the execution of the computer-readable instructions further cause the de-mapper to identify the valid data packet to be played out.

18. The one or more non-transitory computer-readable media of claim 17 , wherein the valid data packet is identified based on at least one of a sequence number or a timestamp associated with a corresponding ROE frame, the sequence number or the timestamp being stored in a RoE header or a mapping table.

19. The one or more non-transitory computer-readable media of claim 15 , wherein the execution of the computer-readable instructions further cause the de-mapper to detect a buffer underrun at the de-mapper.

20. The one or more non-transitory computer-readable media of claim 19 , wherein upon detecting the buffer underrun, the execution of the computer-readable instructions further cause the de-mapper to adjust a re-timer output delay for the buffer using an average data packet delay obtained from an initial CPRI link establishment and an estimated fill time for the buffer.

Assignees

• Cisco Tech Inc

Inventors

• Kumar Manoj
• Malimath Somesh Ubhayanandan
• Anand Prashant

Classifications

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04L69/28 Primary

  Timers or timing mechanisms used in protocols · CPC title

• H04L47/34

  ensuring sequence integrity, e.g. using sequence numbers · CPC title

• H04L49/90 Primary

  Buffering arrangements · CPC title