Level shifter and display device including the same

Patent metadata

Field	Value
Publication number	US-12438545-B2
Application number	US-202318455718-A
Country	US
Kind code	B2
Filing date	Aug 25, 2023
Priority date	Dec 14, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A level shifter includes a first power input terminal to which a first gate voltage may be applied; a second power input terminal to which a second gate voltage may be applied; a third power input terminal to which a third gate voltage may be applied; an output terminal; a first switch element configured to electrically connect the first power input terminal to the output terminal in response to a voltage of on-intervals of a first control signal; a second switch element configured to electrically connect the second power input terminal to the output terminal in response to a voltage of on-intervals of a second control signal; and a third switch element configured to electrically connect the third power input terminal to the output terminal in response to a voltage of on-intervals of a third control signal.

First claim

What is claimed is:

1. A level shifter comprising:
a first power input terminal to which a first gate voltage is applied;
a second power input terminal to which a second gate voltage lower than the first gate voltage is applied;
a third power input terminal to which a third gate voltage lower than the first gate voltage and higher than the second gate voltage is applied;
an output terminal through which a shift clock is outputted;
a first switch element configured to electrically connect the first power input terminal to the output terminal in response to a voltage of on-intervals of a first control signal;
a second switch element configured to electrically connect the second power input terminal to the output terminal in response to a voltage of on-intervals of a second control signal; and
a third switch element configured to electrically connect the third power input terminal to the output terminal in response to a voltage of on-intervals of a third control signal,
wherein a portion of a first on-interval of the third control signal overlaps with a portion of the on-intervals of the first control signal; and
a portion of a second on-interval of the third control signal overlaps with a portion of the on-intervals of the second control signal,
wherein the first on-interval of the third control signal includes:
a first non-overlapping interval not overlapping with the on-interval of the first control signal and the on-interval of the second control signal; and
a first overlapping interval overlapping with a portion of an interval including a rising edge of a pulse among the on-intervals of the first control signal, and
wherein the second on-interval of the third control signal includes:
a second non-overlapping interval not overlapping with the on-interval of the first control signal and the on-interval of the second control signal; and
a second overlapping interval overlapping with a portion of an interval including a rising edge of a pulse among the on-intervals of the second control signal.

2. The level shifter of claim 1 , wherein during the first overlapping interval,
a current flows between the first power input terminal and the output terminal and simultaneously a current flows between the third power input terminal and the output terminal, and
wherein during the second overlapping interval,
a current flows between the second power input terminal and the output terminal and simultaneously a current flows between the third power input terminal and the second power input terminal.

3. The level shifter of claim 1 , further comprising a control part configured to receive a first input clock and a second input clock which has the same frequency as the first input clock and a phase difference with respect to the first input clock, and configured to output the first control signal, the second control signal, and the third control signal.

4. The level shifter of claim 3 , wherein the first overlapping interval and the second overlapping interval are not overlapping with the first input clock and the second input clock, respectively.

5. The level shifter of claim 3 , wherein during the first overlapping interval and the second overlapping interval, a current flows in a power supply wire to which the third gate voltage is applied, and pulses of the first input clock and the second input clock are not inputted in the level shifter.

6. The level shifter of claim 1 , wherein the first non-overlapping interval and the second non-overlapping interval are not overlapping with the on-interval of the first control signal and the on-interval of the second control signal, respectively.

7. The level shifter of claim 1 , wherein the on-interval of the first control signal includes:
the first overlapping interval; and
a third non-overlapping interval not overlapping with the on-interval of the second control signal and the first and second on-intervals of the third control signal, and
wherein the on-interval of the second control signal includes:
the second overlapping interval; and
a fourth non-overlapping interval not overlapping with the on-interval of the first control signal and the first and second on-intervals of the third control signal.

8. A display device comprising:
a display panel on which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are disposed;
a data driver configured to output data signals applied to the data lines;
a gate driver configured to receive a shift clock and supply gate pulses to the gate lines; and
a level shifter configured to receive a first input clock, a second input clock which has the same frequency as the first input clock and a different phase with respect to the first input clock, a first gate voltage, a second gate voltage lower than the first gate voltage, and a third gate voltage having a voltage level between the first gate voltage and the second gate voltage, and configured to output the shift clock,
wherein the level shifter includes:
a first power input terminal to which a first gate voltage is applied;
a second power input terminal to which a second gate voltage is applied;
a third power input terminal to which a third gate voltage is applied;
an output terminal through which the shift clock is outputted;
a controller configured to receive the first input clock and the second input clock and output a first control signal, a second control signal, and a third control signal;
a first switch element configured to electrically connect the first power input terminal to the output terminal in response to a voltage of on-intervals of the first control signal;
a second switch element configured to electrically connect the second power input terminal to the output terminal in response to a voltage of on-intervals of the second control signal; and
a third switch element configured to electrically connect the third power input terminal to the output terminal in response to a voltage of on-intervals of the third control signal, and
wherein a portion of a first on-interval of the third control signal overlaps with a portion of the on-intervals of the first control signal; and
a portion of a second on-interval of the third control signal overlaps with a portion of the on-intervals of the second control signal,

wherein the first on-interval of the third control signal includes:
a first non-overlapping interval not overlapping with the on-interval of the first control signal and the on-interval of the second control signal; and
a first overlapping interval overlapping with a portion of an interval including a rising edge of a pulse among the on-intervals of the first control signal, and
wherein the second on-interval of the third control signal includes:
a second non-overlapping interval not overlapping with the on-interval of the first control signal and the on-interval of the second control signal; and
a second overlapping interval overlapping with a portion of an interval including a rising edge of a pulse among the on-intervals of the second control signal.

9. The display device of claim 8 , wherein during the first overlapping interval,
a current flows between the first power input terminal and the output terminal and simultaneously a current flows between the third power input terminal and the output terminal, and
wherein during the second overlapping interval,
a current flows between the second power input terminal and the output terminal and simultaneously a current flows between the third power input terminal and the second power input terminal.

Assignees

• Lg Display Co Ltd

Inventors

• Jang Hoon
• Hur Jun O
• Kim Dong Ju

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title