Thermal interface materials
US-11811276-B1 · Nov 7, 2023 · US
US12438061B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12438061-B2 |
| Application number | US-202318101051-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 24, 2023 |
| Priority date | May 31, 2022 |
| Publication date | Oct 7, 2025 |
| Grant date | Oct 7, 2025 |
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A method of designing and manufacturing a power electronics converter for an electrical power system is provided. A circuit design for the power electronics converter is selected. A shape constraint for integrating the power electronics converter into the electrical power system is determined, and at least one multi-layer carrier substrate is obtained according to the determined shape constraint. A plurality of power semiconductor prepackages are obtained. Each power semiconductor prepackage includes a power semiconductor switching element embedded in a solid insulating material and an electrical connection extending through the solid insulating material from a terminal of the power semiconductor switching element to a connection surface of the prepackage. The power electronics converter is assembled by forming electrically conductive connections in a z-direction connecting terminals of the power semiconductor switching elements of the power semiconductor prepackages and one or more electrically conductive layers of the multi-layer carrier substrate.
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The invention claimed is: 1. A method of designing and manufacturing a power electronics converter for an electrical power system, the method comprising: selecting a circuit design for the power electronics converter; determining a shape constraint for integrating the power electronics converter into the electrical power system; obtaining a multi-layer carrier substrate according to the determined shape constraint; obtaining a plurality of power semiconductor prepackages, each power semiconductor prepackage of the plurality of power semiconductor prepackages including at least one power semiconductor switching element embedded in a solid insulating material and at least one electrical connection extending through the solid insulating material from at least one terminal of the at least one power semiconductor switching element to a connection surface of the respective power semiconductor prepackage of the plurality of power semiconductor prepackages; and assembling the power electronics converter, the assembling comprising forming electrically conductive connections in a z-direction connecting terminals of the power semiconductor switching elements of the plurality of power semiconductor prepackages and one or more electrically conductive layers of the multi-layer carrier substrate, the z-direction being perpendicular to an x-y plane of the multi-layer carrier substrate and the one or more electrically conductive layers. 2. The method of claim 1 , wherein the shape constraint is a two-dimensional shape constraint. 3. The method of claim 1 , wherein the shape constraint is a three-dimensional shape constraint. 4. The method of claim 3 , wherein the shape constraint includes a plurality of space segments, wherein the multi-layer carrier substrate is obtained according to each space segment of the plurality of space segments. 5. The method of claim 4 , wherein the plurality of space segments are arranged parallelly, vertically adjacent, or parallelly and vertically adjacent. 6. The method of claim 4 , wherein the plurality of space segments are arranged in a non-coplanar manner. 7. The method of claim 6 , wherein the plurality of space segments are arranged along an arcuate line, circumferentially around a component of the electrical power system, or along the arcuate line and circumferentially around the component of the electrical power system. 8. The method of claim 1 , wherein the shape constraint includes a plurality of space segments, wherein the multi-layer carrier substrate is obtained according to each space segment of the plurality of space segments. 9. The method of claim 1 , wherein the shape constraint is defined by an installation space confined by a stator housing, a battery pack housing, a power electronics converter housing, a cooling duct housing, a gas turbine housing, or any combination thereof. 10. The method of claim 1 , wherein assembling the power electronics converter further comprises: arranging the plurality of power semiconductor prepackages on the multi-layer carrier substrate, wherein a position of each power semiconductor prepackage of the plurality of power semiconductor prepackages in the x-y plane meets a position constraint. 11. The method of claim 10 , wherein the position constraint meets a thermal constraint, and wherein the thermal constraint defines: a minimum distance from one power semiconductor prepackage of the plurality of power semiconductor prepackages to a neighboring power semiconductor prepackage of the plurality of power semiconductor prepackages; a maximum distance from one power semiconductor prepackage of the plurality of power semiconductor prepackages to a neighboring power semiconductor prepackage of the plurality of power semiconductor prepackages; or the minimum distance and the maximum distance. 12. The method of claim 11 , wherein the thermal constraint defines the maximum distance, the maximum distance accommodating an optimum heat sink size. 13. The method of claim 1 , wherein each power semiconductor prepackage of the plurality of power semiconductor prepackages is arranged in a grid, in a circular pattern, or in an arcuate or straight line. 14. The method of claim 1 , further comprising: selecting a heat sink for the power electronics converter; forming a thermally conductive connection in the z-direction between a heat removal side of the plurality of power semiconductor prepackages and the heat sink. 15. The method of claim 1 , wherein the electrical power system is an electrical power system for an aircraft. 16. The method of claim 1 , wherein the shape constraint is a shape constraint for integrating the power electronics converter into an electrical propulsion unit (EPU) of an aircraft, the EPU including a propeller or a fan, an electric motor configured to drive rotation of the propeller or the fan, and the power electronics converter connected to the electric motor. 17. The method of claim 1 , wherein each power semiconductor prepackage of the plurality of semiconductor prepackages includes precisely one power semiconductor switching element, and wherein the method further comprises: determining a power rating constraint for the power electronics converter; and selecting a number of power semiconductor prepackages of the plurality of semiconductor prepackages according to the power rating constraint.
Interconnections or connectors in packages · CPC title
of die-attach connectors · CPC title
Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title
characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title
for connecting multiple chips together · CPC title
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