Single crystal semiconductor structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12437988-B2
Application number	US-202418429845-A
Country	US
Kind code	B2
Filing date	Feb 1, 2024
Priority date	Mar 8, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

First claim

What is claimed is:

1. A single crystal semiconductor structure comprising:
a strain compensation layer;
an amorphous substrate on the strain compensation layer;
a lattice matching layer on the amorphous substrate, the lattice matching layer comprising two or more single crystal layers;
a single crystal semiconductor layer on the lattice matching layer; and
a mask pattern between the single crystal semiconductor layer and the lattice matching layer,
wherein the lattice matching layer comprises a direction control film disposed on the amorphous substrate, the direction control film comprising a single crystal structure, and a buffer layer comprising a material different from a material of the direction control film, the buffer layer being disposed on the direction control film and comprising a single crystal structure,
wherein the mask pattern comprises holes exposing the lattice matching layer, and
wherein the single crystal semiconductor layer is disposed on the mask pattern and fills the holes.

2. The single crystal semiconductor structure of claim 1 , wherein the mask pattern comprises silicon nitride or silicon oxide.

3. The single crystal semiconductor structure of claim 1 , wherein the single crystal semiconductor layer is in contact with the lattice matching layer in the holes.

4. The single crystal semiconductor structure of claim 1 , further comprising a heat dispersion layer disposed between the lattice matching layer and the amorphous substrate,
wherein the heat dispersion layer comprises a thermal conductive material.

5. The single crystal semiconductor structure of claim 4 , wherein the heat dispersion layer comprises molybdenum.

6. The single crystal semiconductor structure of claim 4 , further comprising a planarization layer disposed between the heat dispersion layer and the lattice matching layer,
wherein a surface roughness of an upper surface of the planarization layer facing the lattice matching layer is less than a surface roughness of a lower surface of the planarization layer facing the heat dispersion layer.

7. The single crystal semiconductor structure of claim 6 , wherein the planarization layer comprises silicon nitride or silicon oxide.

8. The single crystal semiconductor structure of claim 1 , wherein, a first difference between a coefficient of thermal expansion of the strain compensation layer and a coefficient of thermal expansion of the single crystal semiconductor layer is less than a second difference between a coefficient of thermal expansion of the amorphous substrate and the coefficient of thermal expansion of the single crystal semiconductor layer.

9. The single crystal semiconductor structure of claim 8 , wherein the first difference is equal to or less than 10% of the coefficient of thermal expansion of the single crystal semiconductor layer within a temperature range of about 200° C. to about 1200° C.

10. The single crystal semiconductor structure of claim 9 , wherein the strain compensation layer comprises a molybdenum (Mo) alloy.

11. The single crystal semiconductor structure of claim 1 , wherein a lattice structure of the direction control film matches a lattice structure of the buffer layer.

12. The single crystal semiconductor structure of claim 1 , wherein a crystal of the direction control film is oriented in a ( 111 ) direction.

13. The single crystal semiconductor structure of claim 12 , wherein the direction control film comprises CeO 2 or Sc 2 O 3 .

14. The single crystal semiconductor structure of claim 1 , wherein the buffer layer comprises a single layer comprising MgO or AIN.

15. The single crystal semiconductor structure of claim 1 , wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises CeO 2 or Sc 2 O 3 formed by a deposition process different from a deposition process of the direction control film, and
wherein the second buffer layer comprises MgO or AIN.

16. The single crystal semiconductor structure of claim 1 , wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises MgO or AIN, and
wherein the second buffer layer comprises a same material as a material of the single crystal semiconductor layer.

17. The single crystal semiconductor structure of claim 16 , wherein a crystallinity of the single crystal semiconductor layer is higher than a crystallinity of the second buffer layer.

18. The single crystal semiconductor structure of claim 1 , wherein a thickness of the direction control film is equal to or less than 10 times a critical thickness h c , and wherein the critical thickness h c is determined by a following equation:

h
c

=

[

b

4
⁢

π
⁡
(

1
+
μ

)

⁢

ϵ
0

)

]

[

ln
⁢

(

h
c

b

)

+
1

]

(b: Burgers vector, μ: Poisson's ratio, and ε 0 : a degree of lattice misfit between the direction control film and the single crystal semiconductor layer).

Assignees

• Samsung Electronics Co Ltd
• Ibeam Mat Inc

Inventors

• Choi Junhee
• Matias Vladmir
• Han Joohun

Classifications

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title