Non-volatile memory with slow voltage ramp compensation

Patent metadata

Field	Value
Publication number	US-12437831-B2
Application number	US-202318359816-A
Country	US
Kind code	B2
Filing date	Jul 26, 2023
Priority date	Mar 25, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Non-volatile memory cells are programmed by raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line; programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period; testing, during the first time period, whether the voltage applied to the selected word line is greater than one or more intermediate voltages; and elongating the first time period during the first time period if the voltage applied to the selected word line is not greater than one or more of the intermediate voltages.

First claim

What is claimed is:

1. A non-volatile storage apparatus, comprising:
a signal line;
a plurality of non-volatile memory cells connected to the signal line; and
a control circuit connected to the signal line and the non-volatile memory cells, the control circuit is configured to program the memory cells by raising a voltage applied to the signal line to a program voltage during a first time period and applying the program voltage to the memory cells via the signal line during a second time period after the first time period, the control circuit is further configured to perform testing during the first time period of the voltage applied to the signal line and elongate the first time period during the first time period based on the testing, the testing comprises determining during the first time period whether the voltage applied to the signal line is greater than an intermediate voltage that is lower than the program voltage, the control circuit is configured to elongate the first time period by adding extra time to the first time period if the voltage applied to the signal line is determined during the testing to be not greater than the intermediate voltage.

2. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is further configured to dynamically elongate the first time period during the first time period based on the testing such that different amounts of extra time are added to the first time period to provide more time for raising the voltage applied to the signal line to the program voltage in response to different results of the testing.

3. The non-volatile storage apparatus of claim 1 , wherein:
the testing comprises determining at a first time during the first time period whether the voltage applied to the signal line is greater than a first intermediate voltage that is lower than the program voltage and determining at a second time during the first time period whether the voltage applied to the signal line is greater than a second intermediate voltage that is lower than the program voltage, the second time is after the first time; and
the control circuit is configured to elongate the first time period by:
adding a first amount of extra time to the first time period if the voltage applied to the signal line is determined during the testing to be greater than the first intermediate voltage but not greater than the second intermediate voltage, and
adding a second amount of extra time to the first time period if the voltage applied to the signal line is determined during the testing to be not greater than the first intermediate voltage and not greater than the second intermediate voltage, the second amount of extra time is greater than the first amount of extra time.

4. The non-volatile storage apparatus of claim 3 , wherein:
the second intermediate voltage is greater than the first intermediate voltage.

5. The non-volatile storage apparatus of claim 1 , wherein:
the testing comprises determining during the first time period whether the voltage applied to the signal line is greater than a first testing voltage that is lower than the program voltage and whether the voltage applied to the signal line is greater than a second testing voltage that is higher than the first testing voltage; and
the control circuit is configured to elongate the first time period by:
adding a first amount of extra time to the first time period if the voltage applied to the signal line is determined during the testing to be greater than the first intermediate voltage but not greater than the second intermediate voltage, and
adding a second amount of extra time to the first time period if the voltage applied to the signal line is determined during the testing to be not greater than the first intermediate voltage and not greater than the second intermediate voltage, the second amount of extra time is greater than the first amount of extra time.

6. The non-volatile storage apparatus of claim 5 , wherein:
the second testing voltage is lower than the program voltage.

7. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit includes a charge pump and a testing circuit connected to the charge pump;
the charge pump is configured to perform the raising of the voltage applied to the signal line to a program voltage; and
the testing circuit is configured to perform the testing.

8. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to elongate the first time period by adding an amount of extra time to the first time period based on a number of program/erase cycles performed for the memory cells.

9. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is further configured to lower the voltage applied to the signal line from the program voltage to ground during a third time period after the second time period; and
the control circuit is further configured to perform program verify for the memory cells during a fourth time period after the third time period.

10. The non-volatile storage apparatus of claim 9 , wherein:
the control circuit is configured to raise the voltage applied to the signal line to the program voltage during the first time period, apply the program voltage to the memory cells via the signal line during the second time period and lower the voltage applied to the signal line from the program voltage to ground during the third time period in order to apply a program voltage pulse comprising the program voltage to the memory cells via the signal line.

11. A method, comprising:
raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line;
programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period;
performing program verify for the selected non-volatile memory cells during an additional time period after the second time period;
testing the voltage applied to the selected word line during the first time period including determining, during the first time period, whether the voltage applied to the selected word line is greater than an intermediate voltage that is lower than the program voltage; and
elongating the first time period during the first time period based on the testing including adding extra time to the first time period if the voltage applied to the selected word line is determined to be not greater than the intermediate voltage during the testing.

12. The method of claim 11 , wherein:
the elongating the first time period comprises dynamically elongating the first time period during the first time period based on the testing such that different amounts of extra time are added to the first time period to provide more time for raising the voltage applied to the selected word line to the program voltage in response to different results of the testing.

13. The method of claim 11 , wherein:
the testing comprises determining, during the first time period, whether the voltage applied to the selected word line is greater than a first intermediate voltage that is lower than the program voltage and a second intermediate voltage that is greater than the first intermediate voltage; and
the elongating comprises:
adding a first amount of extra time to the first time period if the voltage applied to the selected word line is determined during the testing to be greater than the first intermediate voltage but not greater than the second intermediate voltage, and
adding a second amount of extra time to the first time period if t

Assignees

• Sandisk Technologies Inc

Inventors

• Thoppa Sai Gautham
• Amin Parth
• Pham Long

Classifications

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title

• G11C29/46 Primary

  Test trigger logic · CPC title