Memory including thermal anneal circuits and methods for operating the same

Patent metadata

Field	Value
Publication number	US-12437820-B2
Application number	US-202318199308-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	May 18, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

First claim

What is claimed is:

1. A memory, comprising:
an array of memory cells;
a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells, the group of memory cells including multiple three-dimensional (3D) stacks of memory cells having multiple levels;
a capacitor;
a circuit to cause discharge of the capacitor via the resistive component; and
a decoder to connect the capacitor to selected resistive components of a plurality of resistive components including the resistive component,
wherein the resistive component includes upper heating plates located above the 3D stacks of memory cells, lower heating plates located below the 3D stacks of memory cells and conductive vertical pillars connecting the upper heating plates to the lower heating plates, wherein an arrangement of the upper heating plates, the lower heating plates and the conductive vertical pillars provides a single continuous snake-shaped heating element to provide heat to each 3D stack of memory cells of the group of memory cells in thermal communication with the resistive component.

2. The memory of claim 1 , further comprising:
a charge pump; and
a circuit to enable the charge pump to precharge the capacitor.

3. The memory of claim 1 , including a plurality of groups of memory cells in the array of memory cells, including the group of memory cells, wherein each of the plurality of resistive components is disposed in thermal communication with respective groups of memory cells of the plurality of groups of memory cells.

4. The memory of claim 1 , wherein the capacitor has a capacitance greater than 10 nF.

5. The memory of claim 1 , including a controller configured to execute erase operations for memory cells in the array, and to control the circuit to enable discharge of the capacitor to induce current in the resistive component of the group of memory cells in timing coordination with an erase operation to erase the group of memory cells.

6. The memory of claim 1 , wherein the group of memory cells is disposed in a specific block of the array of memory cells, the specific block including one or more segments, each segment including a plurality of word line layers and a plurality of bit line pillars disposed through the plurality of word line layers.

7. The memory of claim 1 , including a plurality of groups of memory cells including the group of memory cells, the groups in the plurality of groups disposed in respective specific blocks in a plurality of specific blocks of the array of memory cells, each specific block including one or more segments, each segment including a plurality of word line layers and a plurality of bit line pillars disposed through the plurality of word line layers.

8. The memory of claim 7 , wherein the plurality of specific blocks are arranged in rows having a first width orthogonal to the rows, with inactive structures between the rows having a second width greater than five times the first width.

9. The memory of claim 7 , wherein segments in the plurality of specific blocks are arranged in rows having a first width orthogonal to the rows, with inactive structures between the rows having a second width greater than ten times the first width.

10. The memory of claim 7 , wherein the array includes a plurality of erase blocks configured for block erase operations, and wherein a particular erase block in the plurality of erase blocks includes more than one specific block in the plurality of specific blocks.

11. The memory of claim 7 , wherein each of the plurality of resistive components is disposed in thermal communication with respective groups of memory cells in the plurality of groups of memory cells.

12. The memory of claim 7 , wherein the capacitor comprises a plurality of layers of conductors separated by insulating layers, with conductors in layers in the plurality of layers connected to form a first terminal of the capacitor interleaved with conductors in layers in the plurality of layers connected to form a second terminal of the capacitor.

13. The memory of claim 12 , wherein the plurality of specific blocks and the capacitor are disposed on a single integrated circuit chip.

14. The memory of claim 1 , wherein the group of memory cells and the capacitor are disposed on a single integrated circuit chip.

15. A method for operating a memory, the memory including a plurality of groups of memory cells, the method comprising:
charging a capacitor;
using a decoder to select a group of memory cells of the plurality of groups of memory cells, the selected group of memory cells including multiple three-dimensional (3D) stacks of memory cells having multiple levels; and
applying discharge current from the capacitor to a resistive component in thermal communication with the selected group of memory cells,
wherein the resistive component includes upper heating plates located above the 3D stacks of memory cells, lower heating plates located below the 3D stacks of memory cells and conductive vertical pillars connecting the upper heating plates to the lower heating plates, wherein an arrangement of the upper heating plates, the lower heating plates and the conductive vertical pillars provides a single continuous snake-shaped heating element to provide heat to each 3D stack of memory cells of the group of memory cells in thermal communication with the resistive component.

16. The method of claim 15 , including:
executing an erase operation to erase the selected group of memory cells; and
applying the discharge current in timing coordination with the erase operation.

17. The method of claim 15 , including:
executing an erase operation to erase the selected group of memory cells; and
the applying of the discharge current triggered by the erase operation.

18. A memory, comprising:
an array of memory cells including a plurality of groups of memory cells, the groups in the plurality of groups being disposed in respective specific blocks in a plurality of specific blocks of the array of memory cells, each specific block including one or more segments, each segment including a plurality of word line layers and a plurality of bit line pillars disposed through the plurality of word line layers;
a resistive component disposed in thermal communication with a group of memory cells of the plurality of groups of memory cells;
a capacitor; and
a circuit to cause discharge of the capacitor via the resistive component,
wherein, at least one of (i) the plurality of specific blocks are arranged in rows having a first block width orthogonal to the rows of specific blocks, with inactive structures between the rows of specific blocks having a second block width greater than five times the first block width and (ii) segments in the plurality of specific blocks are arranged in rows having a first segment width orthogonal to the rows of segments, with inactive structures between the rows of segments having a second segment width greater than ten times the first segment width.

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting
• Yeh Teng-Hao
• Chen Wei-Chen

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title