Pixel and display apparatus

Patent metadata

Field	Value
Publication number	US-12437717-B2
Application number	US-202318525303-A
Country	US
Kind code	B2
Filing date	Nov 30, 2023
Priority date	Mar 24, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A pixel in which a luminance difference may be reduced during low-frequency driving, and a display apparatus including the same, there is provided a pixel that operates at a first scanning rate in a first mode and operates at a second scanning rate in a second mode, wherein the pixel includes a display element having an anode and a cathode, a first transistor that controls the magnitude of a driving current flowing to the display element according to a gate-source voltage, and a second transistor that is in an off state in the first mode and transmits a bias voltage to the first transistor in response to a first scan signal in the second mode.

First claim

What is claimed is:

1. A pixel that operates at a first scanning rate in a first mode and operates at a second scanning rate in a second mode, the pixel comprising:
a display element having an anode and a cathode;
a first transistor that controls a magnitude of a driving current flowing to the display element according to a gate-source voltage; and
a second transistor that is in an off state during all frame periods in the first mode and transmits a bias voltage to the first transistor in response to a first scan signal in the second mode.

2. The pixel of claim 1 , wherein the second scanning rate is smaller than the first scanning rate.

3. The pixel of claim 1 , wherein one frame period in the second mode comprises a display scanning period and a self-scanning period, and
the first scan signal has a voltage at a turn-off level throughout the display scanning period and has a pulse at a turn-on level throughout the self-scanning period.

4. The pixel of claim 3 , wherein a width of a pulse voltage at the turn-on level is greater than one horizontal scanning period (1H).

5. The pixel of claim 1 , further comprising:
a first capacitor connected to a gate of the first transistor;
a third transistor that transmits a data voltage to a source of the first transistor in response to a second scan signal; and
a fourth transistor that transmits a first initialization voltage to the anode of the display element in response to a third scan signal,
wherein the second transistor transmits the bias voltage to the source of the first transistor in response to the first scan signal in the second mode.

6. The pixel of claim 5 , wherein one frame period in the second mode comprises a display scanning period and a self-scanning period,
the first scan signal has a voltage at a turn-off level throughout the display scanning period and has a first pulse at a turn-on level throughout the self-scanning period,
the second scan signal has second pulses at the turn-on level within the display scanning period and within the self-scanning period, and
the third scan signal has third pulses at the turn-on level within the display scanning period and within the self-scanning period.

7. The pixel of claim 6 , wherein a width of the first pulse is greater than a width of each of the second pulses and a width of each of the third pulses.

8. The pixel of claim 6 , wherein an interval between a falling edge of one of the second pulses and a falling edge of a corresponding one of the third pulses is one horizontal scanning period (1H).

9. The pixel of claim 6 , wherein the data voltage transmitted to the source of the first transistor within the self-scanning period is substantially the same as the bias voltage.

10. The pixel of claim 5 , wherein a level of the bias voltage is greater than a level of the first initialization voltage.

11. The pixel of claim 5 , further comprising a fifth transistor that connects the gate of the first transistor and a drain of the first transistor with each other in response to a fourth scan signal,
wherein one frame period in the second mode comprises a display scanning period and a self-scanning period, and
the fourth scan signal has a fourth pulse at a turn-on level within the display scanning period and has a voltage at a turn-off level throughout the self-scanning period.

12. The pixel of claim 11 , further comprising a sixth transistor that transmits a second initialization voltage to the gate of the first transistor in response to a fifth scan signal,
wherein the fifth scan signal has a fifth pulse at the turn-on level in the display scanning period and has a voltage at the turn-off level during the self-scanning period.

13. The pixel of claim 12 , wherein the second scan signal has multiple second pulses at the turn-on level within the display scanning period and within the self-scanning period, and
a width of the fourth pulse is substantially equal to a width of each of the second pulses and a width of the fifth pulse.

14. The pixel of claim 5 , further comprising a second capacitor connected to the source of the first transistor.

15. A pixel that operates at a first scanning rate in a first mode, operates at a second scanning rate in a second mode, and is connected to a first scan line, a second scan line, a third scan line, a fourth scan line and a fifth scan line that transmit a first scan signal, a second scan signal, a third scan signal, a fourth scan signal and a fifth scan signal, respectively, an emission control line that transmits an emission control signal, a data line that transmits a data voltage, a power line that transmits a driving voltage, and a first voltage line, a second voltage line and a third voltage line that transmits a first initialization voltage, a second initialization voltage, and a bias voltage, respectively, the pixel comprising:
a display element having an anode and a cathode;
a first capacitor having a first electrode connected to the power line, and a second electrode;
a first transistor having a gate connected to the second electrode of the first capacitor, a source connected to the power line, and a drain connected to the anode of the display element;
a second transistor having a gate connected to the first scan line, a source connected to the data line, and a drain connected to the source of the first transistor;
a third transistor having a gate connected to the second scan line, a source connected to the drain of the first transistor, and a drain connected to the gate of the first transistor;
a fourth transistor having a gate connected to the third scan line, a source connected to the gate of the first transistor, and a drain connected to the first voltage line;
a fifth transistor having a gate connected to the emission control line, a source connected to the power line, and a drain connected to the source of the first transistor;
a sixth transistor having a gate connected to the emission control line, a source connected to the drain of the first transistor, and a drain connected to the anode of the display element;
a seventh transistor having a gate connected to the fourth scan line, a source connected to the anode of the display element, and a drain connected to the second voltage line; and
an eighth transistor having a gate connected to the fifth scan line, a source connected to the third voltage line, and a drain connected to the source of the first transistor, and being in an off state during all frame periods in the first mode.

16. The pixel of claim 15 , wherein the second scanning rate is smaller than the first scanning rate.

17. The pixel of claim 15 , further comprising a second capacitor having a third electrode connected to the power line, and a fourth electrode connected to the source of the first transistor.

18. The pixel of claim 15 , wherein the one frame period in the second mode comprises a display scanning period and a self-scanning period,
first pulses at a turn-on level are applied to the first scan line within the display scanning period and within the self-scanning period,
a second pulse at the turn-on level is applied to the second scan line within the display scanning period, and a voltage at a turn-off level is applied to the second scan line throughout the self-scanning period,
a third pulse at the turn-on level is applied to the third scan line within the display scanning period, and a voltage at the turn-off level is applied to the third scan line throughout the self-scanning period,
fourth pulses at the turn-on level are applied to the fourth scan line

Assignees

• Samsung Display Co Ltd

Inventors

• An Jinsung
• Kim Sungho
• Kim Yongjae
• Shin Yoonjee
• Jung Sugwoo

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title