Pixel drive circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-12437697-B2
Application number	US-202218290015-A
Country	US
Kind code	B2
Filing date	Nov 23, 2022
Priority date	Nov 23, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.

First claim

What is claimed is:

1. A pixel drive circuit, comprising:
a plurality of scan drive circuits cascaded in a pixel column direction, wherein the plurality of scan drive circuits are coupled to a plurality of rows of pixels via a plurality of gate lines; and each of the scan drive circuits is further coupled to a scan drive line and is configured to transmit a gate drive signal to a gate line coupled to the scan drive circuit based on a drive signal provided by the scan drive line;
a plurality of emission drive circuits cascaded in the pixel column direction, wherein the plurality of emission drive circuits are coupled to the plurality of rows of pixels via a plurality of emission control lines; and each of the emission drive circuits is further coupled to an emission drive line and is configured to transmit an emission control signal to an emission control line coupled to the emission drive circuit based on a drive signal provided by the emission drive line;
a plurality of compensation drive circuits cascaded in the pixel column direction, wherein the plurality of compensation drive circuits are coupled to the plurality of rows of pixels via a plurality of compensation lines; and each of the compensation drive circuits is further coupled to a compensation drive line and is configured to transmit a compensation signal to a compensation line coupled to the compensation drive circuit based on a drive signal provided by the compensation drive line; and
a plurality of reset drive circuits cascaded in the pixel column direction, wherein the plurality of reset drive circuits are coupled to the plurality of rows of pixels via a plurality of reset lines; and each of the reset drive circuits is further coupled to a reset drive line and is configured to transmit a reset signal to a reset line coupled to the reset drive circuit based on a drive signal provided by the reset drive line;
wherein a scan drive circuit, a emission drive circuit, a compensation drive circuit, and a reset drive circuit that are coupled to a same row of pixels are arranged sequentially in a pixel row direction, and the scan drive circuit is disposed on a side distal to the pixels; and among signal lines as coupled in the pixel drive circuit, a plurality of the signal lines is overlapped with each other, and cutouts are provided at overlapping portions of the plurality of signal lines.

2. The pixel drive circuit according to claim 1 , wherein along the pixel row direction, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit that are coupled to the same row of pixels are arranged sequentially in a direction proximal to the pixels.

3. The pixel drive circuit according to claim 1 , wherein each of the scan drive line, the emission drive line, the compensation drive line, and the reset drive line comprises: a direct current (DC) drive line for providing a direct current signal and an alternating current (AC) drive line for providing an alternating current signal; and
for the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit, the DC drive line coupled to each drive circuit is disposed on both sides of the drive circuit in the pixel row direction, and the AC drive line coupled to each drive circuit is disposed on one side distal to the drive circuit of the DC drive line.

4. The pixel drive circuit according to claim 3 , wherein the pixel drive circuit and the pixels are both disposed on a same side of a substrate; and
each of the drive lines comprises: a plurality of metal layers sequentially stacked along a direction away from the substrate, and an insulating layer further disposed between every two adjacent metal layers, every two adjacent metal layers being interconnected through a via hole penetrating through the insulating layer.

5. The pixel drive circuit according to claim 4 , wherein each of the drive lines comprises: two metal layers sequentially stacked along the direction away from the substrate.

6. The pixel drive circuit according to claim 5 , wherein the pixel comprises a gate (GATE) metal layer, an inter-layer di-electric (ILD) layer, and a source-drain (SD) metal layer sequentially stacked along a direction away from the substrate; and
for the two metal layers, one metal layer is disposed on a same layer as the GATE metal layer, and the other metal layer is disposed on a same layer as the SD metal layer; and the insulating layer between the two metal layers is disposed on a same layer as the ILD layer.

7. The pixel drive circuit according to claim 6 , wherein the cutout is provided on the GATE metal layer.

8. The pixel drive circuit according to claim 1 , wherein the plurality of scan drive circuits are coupled to the plurality of rows of pixels in one-to-one correspondence;
the plurality of emission drive circuits are coupled to the plurality of rows of pixels in one-to-one correspondence, or each of the emission drive circuits is coupled to at least two rows of pixels;
the plurality of compensation drive circuits are coupled to the plurality of rows of pixels in one-to-one correspondence, or each of the compensation drive circuits is coupled to at least two rows of pixels; and
the plurality of reset drive circuits are coupled to the plurality of rows of pixels in one-to-one correspondence, or each of the reset drive circuits is coupled to at least two rows of pixels.

9. The pixel drive circuit according to claim 8 , wherein each of the emission drive circuits is coupled to two adjacent rows of pixels or four adjacent rows of pixels;
each of the compensation drive circuits is coupled to two adjacent rows of pixels or four adjacent rows of pixels; and
each of the reset drive circuits is coupled to two adjacent rows of pixels or four adjacent rows of pixels.

10. The pixel drive circuit according to claim 9 , wherein each of the emission drive circuits is coupled to two adjacent rows of pixels, each of the compensation drive circuits is coupled to two adjacent rows of pixels, and each of the reset drive circuits is coupled to two adjacent rows of pixels;
for every two adjacent rows of pixels, in the pixel column direction, a total width of two scan drive circuits coupled to the two rows of pixels in one-to-one correspondence is equal to a width of one emission drive circuit coupled to the two rows of pixels, is equal to a width of one compensation drive circuit coupled to the two rows of pixels, and is equal to a width of one reset drive circuit coupled to the two rows of pixels; and
in the pixel row direction, a length of the scan drive circuit is greater than a length of the emission drive circuit, greater than a length of the compensation drive circuit, and greater than a length of the reset drive circuit; the length of the compensation drive circuit is equal to the length of the reset drive circuit and greater than the length of the emission drive circuit; and the compensation drive circuit has a same structure as the reset drive circuit.

11. The pixel drive circuit according to claim 1 , wherein each of the emission drive circuit, the compensation drive circuit, and the reset drive circuit comprises: an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, and an anti-creeping pull-down sub-circuit; and wherein
the input sub-circuit is respectively coupled to a first clock terminal, an input terminal, and a pull-up node, and is configured to control a potential of the pull-up node based on a first clock signal provided by the first clock terminal and an input signal provided by the input terminal;
the output sub-circuit is respectively coupled to the pull-up node, a first power su

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhao Donghui
• Xu Pan
• Han Ying
• Zhang Xing
• Luo Chengyuan
• Lv Guangshuang
• Yao Xing
• Zhou Dandan
• Liu Miao

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title