Method and apparatus of designing integrated circuit

Patent metadata

Field	Value
Publication number	US-12437137-B2
Application number	US-202217805931-A
Country	US
Kind code	B2
Filing date	Jun 8, 2022
Priority date	Jul 8, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A method and an apparatus of designing an integrated circuit are provided. The method includes: S1, loading a power fill to a circuit layout with original metal lines; S2, checking whether a current layout includes a region with a spacing error; if yes, performing S3; otherwise, outputting the current layout; and S3, pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width delta, and returning to the S2.

First claim

The invention claimed is:

1. A method of designing an integrated circuit, comprising:
S1: loading a power fill to a layout with original metal lines;
S2: checking whether a current layout comprises a region with a spacing error;
when yes, performing S3; otherwise, outputting the current layout; and
S3: pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width, and returning to the S2;
wherein the S2 further comprises:
after the region with a spacing error is detected, identifying an error type of the region with a spacing error, wherein the error types comprise:
a first error type: two metal edges of the region with a spacing error are both formed by original metal lines;
a second error type: two metal edges of the region with a spacing error are both formed by power fill shapes; and
a third error type: one of two metal edges of the region with a spacing error is formed by a power fill shape, and the other of two metal edges is formed by an original metal line;
when the error type is the first error type, searching for a power fill shape connected to a first metal edge along a direction perpendicular to the first metal edge and a power fill shape connected to a second metal edge along a direction perpendicular to the second metal edge, and pruning the power fill shapes by a total of the predetermined spacing width.

2. The method of designing an integrated circuit according to claim 1 , wherein the S2 comprises:
checking whether a spacing between adjacent metal lines in the current layout is less than a minimum spacing threshold, and when yes, determining a region as the region with a spacing error.

3. The method of designing an integrated circuit according to claim 1 , wherein the power fill shape connected to the first metal edge and the power fill shape connected to the second metal edge are pruned by a half of the predetermined spacing width respectively.

4. The method of designing an integrated circuit according to claim 1 , when the error type is the second error type, pruning the power fill shapes forming the two metal edges by a half of the predetermined spacing width respectively.

5. The method of designing an integrated circuit according to claim 1 , when the error type is the third error type, pruning the power fill shape forming the one of two metal edges by the predetermined spacing width.

6. The method of designing an integrated circuit according to claim 5 , when the error type is the third error type, searching for a power fill shape connected to the other of two metal edges along a direction perpendicular to the other of two metal edges, and pruning the power fill shape connected to the other of two metal edges and the power fill shape forming the one of two metal edges by a half of the predetermined spacing width respectively.

7. The method of designing an integrated circuit according to claim 1 , wherein the S2 comprises:
when it is detected that a total number of the spacing error of the first error type, the second error type or the third error type is greater than 0, determining that the current layout comprises the region with a spacing error, and performing the S3.

8. The method of designing an integrated circuit according to claim 1 ,
wherein the predetermined spacing width is less than 1/20 to ½ of a minimum spacing threshold.

9. An apparatus of designing an integrated circuit, comprising:
one or more processors; and
a storage apparatus, configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to execute operations of:
loading a power fill to a layout;
checking whether a current layout comprises a region with a spacing error, when yes, repairing the region with a spacing error; otherwise, outputting a repaired layout;
after the region with a spacing error is detected, identifying an error type of the region with a spacing error, wherein the error types comprise:
a first error type: two metal edges of the region with a spacing error are both formed by original metal lines;
a second error type: two metal edges of the region with a spacing error are both formed by power fill shapes; and
a third error type: one of two metal edges of the region with a spacing error is formed by a power fill shape, and the other of two metal edges is formed by an original metal line;
when the error type is the first error type, searching for a power fill shape connected to a first metal edge along a direction perpendicular to the first metal edge and a power fill shape connected to a second metal edge along a direction perpendicular to the second metal edge, and pruning the power fill shapes by a total of the predetermined spacing width; and
pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width, and outputting the current layout after the pruning to the checking whether a current layout comprises a region with a spacing error.

10. The apparatus of designing an integrated circuit according to claim 9 , wherein the one or more programs cause the one or more processors to execute operations of:
checking whether a spacing between metal lines tangent to a region in the current layout is less than a minimum spacing threshold, and when yes, determining the region as the region with a spacing error.

11. The apparatus of designing an integrated circuit according to claim 9 , wherein the one or more programs cause the one or more processors to execute operations of: pruning the power fill shape connected to the first metal edge and the power fill shape connected to the second metal edge by a half of the predetermined spacing width respectively.

12. The apparatus of designing an integrated circuit according to claim 10 , wherein the one or more programs cause the one or more processors to execute operations of: when an error type is a second error type, pruning power fill shapes forming two metal edges by a half of the predetermined spacing width respectively.

13. The apparatus of designing an integrated circuit according to claim 12 , wherein the one or more programs cause the one or more processors to execute operations of: when the error type is a third error type, pruning a power fill shape forming one of two metal edges by the predetermined spacing width.

14. The apparatus of designing an integrated circuit according to claim 12 , wherein the one or more programs cause the one or more processors to execute operations of: when the error type is a third error type, searching for a power fill shape connected to the other of two metal edges along a direction perpendicular to the other of two metal edges, and pruning the power fill shape connected to the other of two metal edges and a power fill shape forming one of two metal edges by a half of the predetermined spacing width respectively.

15. The apparatus of designing an integrated circuit according to claim 9 , wherein the one or more programs cause the one or more processors to execute operations of: when it is detected that a total number of the spacing error of a first error type, a second error type or a third error type is greater than 0, determining that the current layout comprises the region with a spacing error, and starts the pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width, and outputting the current layout after the pruning to the checking whether a current layout comprises a region with a spacing error.

16. The apparatus of designing an integrated circuit acco

Assignees

• Changxin Memory Tech Inc

Inventors

• Chen Chuanjiang
• Tang Li
• Bai Li
• Zhao Kang

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title