Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Patent metadata

Field	Value
Publication number	US-12436907-B2
Application number	US-202318482268-A
Country	US
Kind code	B2
Filing date	Oct 6, 2023
Priority date	Dec 19, 2014
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

First claim

What is claimed is:

1. A memory stack comprising:
a first memory die comprising:
a first set of memory cells;
a first data interface;
a second data interface; and
first steering circuitry coupled to the first set of memory cells, the first data interface, and the second data interface; and

a second memory die comprising:
a second set of memory cells;
a third data interface;
a fourth data interface coupled to the second data interface using a first set of through-silicon-via (TSV) connections; and
second steering circuitry coupled to the second set of memory cells, the third data interface, and the fourth data interface, wherein the first memory die and the second memory die are homogeneous.

2. The memory stack of claim 1 , wherein the memory stack is part of a memory package comprising a package substrate comprising at least two data interfaces, wherein the first data interface and the third data interface are coupled to the at least two data interfaces of the package substrate.

3. The memory stack of claim 1 , wherein the first memory die comprises a command and address (CA) interface coupled to the first set of memory cells.

4. The memory stack of claim 1 , wherein the first steering circuitry comprises:
a receiver coupled to a first set of ports of the first data interface;
a transmitter coupled to the first set of ports; and
a set of multiplexers coupled between the receiver, the transmitter, a second set of ports of the second data interface, and the first set of memory cells.

5. The memory stack of claim 4 , wherein the set of multiplexers is to selectively connect a first path between the receiver and the first set of memory cells, a second path between the receiver and the second set of ports, a third path between the first set of memory cells and the transmitter, and a fourth path between the first set of memory cells and the transmitter.

6. The memory stack of claim 4 , wherein the first steering circuitry further comprises a delay element.

7. The memory stack of claim 1 , wherein:
the first memory die further comprises a fifth data interface; and
the second memory die further comprises a sixth data interface coupled to the fifth data interface using a second set of TSV connections.

8. The memory stack of claim 1 , wherein:
the first steering circuitry comprises:
a first receiver coupled to a first set of ports of the first data interface to couple to a first set of data lines arranged into a first nibble; and
a first transmitter coupled to the first set of ports;

the second steering circuitry comprises:
a second receiver coupled to a second set of ports of the third data interface to couple to a second set of data lines arranged into a second nibble; and
a second transmitter coupled to the second set of ports.

9. A memory package comprising:
a package substrate comprising at least two package interfaces; and
a dual-ported stack comprising a plurality of homogeneous memory devices stacked on the package substrate, wherein:
a first memory device of the plurality of homogeneous memory devices comprises:
a first set of memory cells;
a first data interface;
a second data interface; and
first steering circuitry coupled to the first set of memory cells, the first data interface, and the second data interface; and

a second memory device of the plurality of homogeneous memory devices comprises:
a second set of memory cells;
a third data interface;
a fourth data interface coupled to the second data interface using a first set of through-silicon-via (TSV) connections; and
second steering circuitry coupled to the second set of memory cells, the third data interface, and the fourth data interface.

10. The memory package of claim 9 , wherein the first memory device comprises a command and address (CA) interface coupled to the first set of memory cells.

11. The memory package of claim 9 , wherein the first steering circuitry comprises:
a receiver coupled to a first set of ports of the first data interface;
a transmitter coupled to the first set of ports; and
a set of multiplexers coupled between the receiver, the transmitter, a second set of ports of the second data interface, and the first set of memory cells.

12. The memory package of claim 11 , wherein the set of multiplexers is to selectively connect a first path between the receiver and the first set of memory cells, a second path between the receiver and the second set of ports, a third path between the first set of memory cells and the transmitter, and a fourth path between the first set of memory cells and the transmitter.

13. The memory package of claim 11 , wherein the first steering circuitry further comprises a delay element.

14. The memory package of claim 9 , wherein:
the first memory device further comprises a fifth data interface; and
the second memory device further comprises a sixth data interface coupled to the fifth data interface using a second set of TSV connections.

15. The memory package of claim 9 , wherein:
the first steering circuitry comprises:
a first receiver coupled to a first set of ports of the first data interface to couple to a first set of data lines arranged into a first nibble; and
a first transmitter coupled to the first set of ports;

the second steering circuitry comprises:
a second receiver coupled to a second set of ports of the third data interface to couple to a second set of data lines arranged into a second nibble; and
a second transmitter coupled to the second set of ports.

16. A memory package comprising:
a package substrate comprising at least two data interfaces; and
a stack of memory devices stacked on the package substrate, wherein the memory devices of the stack are homogeneous, wherein:
a first memory device of the stack of memory devices comprises:
a first set of memory cells;
a first data interface;
a second data interface; and
first steering circuitry coupled to the first set of memory cells, the first data interface, and the second data interface; and

a second memory device of the stack of memory devices comprises:
a second set of memory cells;
a third data interface;
a fourth data interface coupled to the second data interface using a first set of through-silicon-via (TSV) connections; and
second steering circuitry coupled to the second set of memory cells, the third data interface, and the fourth data interface.

17. The memory package of claim 16 , wherein the first memory device comprises a command and address (CA) interface coupled to the first set of memory cells.

18. The memory package of claim 16 , wherein the first steering circuitry comprises:
a receiver coupled to a first set of ports of the first data interface;
a transmitter coupled to the first set of ports; and
a set of multiplexers coupled between the receiver, the transmitter, a second set of ports of the second data interface, and the first set of memory cells.

19. The memory package of claim 18 , wherein the set of multiplexers is to selectively connect a first path between the receiver and the first set of memory cells, a second path between the receiver and the second set of ports, a third path between the first set of memory cells and the transmitter, and a fourth path between the first set of memory cells and the transmitter.

20. The memory package of claim 16 , wherein:
the first steering circuitry comprises:
a first receiver coupled to a first set of ports of the first data interface to couple to a first set of data lines arrange

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Linstadt John Eric
• Giovannini Thomas J
• Wright Kenneth L

Classifications

• G06F2213/28

  DMA · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title