Cache circuit that selectively stores data blocks to dynamically optimize for read and write transactions

Patent metadata

Field	Value
Publication number	US-12436889-B1
Application number	US-202418793111-A
Country	US
Kind code	B1
Filing date	Aug 2, 2024
Priority date	Aug 2, 2024
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A cache circuit includes read address registers to store memory addresses of data blocks requested in recent memory read transactions in a memory circuit and write address registers to store memory addresses of the data blocks recently written to the memory circuit. The cache circuit also includes data registers for storing data blocks corresponding to select memory addresses stored in the read address registers and the write address registers based on a pattern of recent memory transactions. The selection of memory addresses for which corresponding data blocks are stored in the data registers is based on a mode count that may be dynamically determined based on the memory addresses accessed in the most recent memory transactions. The mode count depends on whether a requested data block is stored in the data registers and whether the memory address is stored in the read address registers or the write address registers.

First claim

What is claimed is:

1. A cache circuit configured to couple to a memory circuit, the cache circuit comprising:
a plurality of read address registers configured to store memory addresses of data blocks requested from a memory circuit in most recent memory read transactions;
a plurality of write address registers configured to store memory addresses of data blocks written to the memory circuit in most recent memory write transactions;
a plurality of data registers configured to selectively store, based on a mode count, the data blocks requested from the memory circuit in the most recent memory read transactions and the data blocks written to the memory circuit in the most recent memory write transactions; and
a control circuit configured to:
receive a first memory read transaction requesting a first data block at a first memory address;
generate a hit signal in an active state in response to determining that the first data block is stored in the plurality of data registers;
return the first data block from the plurality of data registers in response to the hit signal; and
adjust the mode count based on the first memory address.

2. The cache circuit of claim 1 , wherein:
the plurality of data registers stores a first number N of the data blocks requested from the memory circuit in the most recent memory read transactions and written to the memory circuit in the most recent memory write transactions;
the plurality of read address registers stores memory addresses of N most recent memory read transactions; and
the plurality of write address registers stores memory addresses of N most recent memory write transactions.

3. The cache circuit of claim 2 , wherein:
a second number L of the data registers in the plurality of data registers store data blocks corresponding to memory addresses stored in the plurality of read address registers;
a third number N-L of the data registers in the plurality of data registers store data blocks corresponding to memory addresses stored in the plurality of write address registers; and
the second number L is adjusted from zero (0) to N depending on the mode count.

4. The cache circuit of claim 3 , wherein:
in response to the mode count being between a positive threshold and a negative threshold, the second number L is unchanged;
in response to the mode count being greater than the positive threshold, the second number L is increased; and
in response to the mode count being less than the negative threshold, the second number L is decreased.

5. The cache circuit of claim 1 , wherein the control circuit is further configured to:
in response to the hit signal being in the active state, decrease an absolute value of the mode count;
determine whether the first memory address matches a memory address in either the plurality of read address registers or the plurality of write address registers; and
in response to the hit signal being in an inactive state:
decrease the mode count in response to determining the first memory address matches a memory address in either the plurality of read address registers or the plurality of write address registers; and
increase the mode count in response to determining the first memory address does not match a memory address in either the plurality of read address registers or the plurality of write address registers.

6. The cache circuit of claim 1 , the control circuit further comprising:
a first comparator configured to compare the first memory address to the memory addresses stored in each of the plurality of read address registers; and
a second comparator configured to compare the first memory address to the memory addresses stored in each of the plurality of write address registers.

7. The cache circuit of claim 6 , the control circuit further comprising:
a first plurality of indicators, each corresponding to a read address register of the plurality of read address registers and each configured to indicate whether a first data block corresponding to the memory address in the read address register is stored in the plurality of data registers; and
a second plurality of indicators, each corresponding to a write address register of the plurality of write address registers and each configured to indicate whether a second data block corresponding to the memory address in the corresponding write address register is stored in the plurality of data registers;
wherein the control circuit is further configured to generate the hit signal in the active state in response to:
the first comparator indicating that the first memory address matches a second memory address in a read address register of the plurality of read address registers, and the first plurality of indicators indicates that the second memory address corresponds to one of the data blocks stored in the plurality of data registers; or
the second comparator indicating that the first memory address matches a third memory address in a write address register of the plurality of write address registers, and the second plurality of indicators indicates that the third memory address corresponds to one of the data blocks stored in the plurality of data registers.

8. The cache circuit of claim 1 , the control circuit further configured to:
generate the hit signal in an inactive state in response to determining that the first data block is not stored in the plurality of data registers.

9. The cache circuit of claim 4 , wherein the control circuit is programmable to store the positive threshold and the negative threshold.

10. The cache circuit of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

11. An integrated circuit (IC) comprising:
a memory circuit;
a plurality of processors configured to access write data blocks to the memory circuit and read data blocks from the memory circuit; and
a cache circuit coupled to the memory circuit, the cache circuit comprising:
a plurality of read address registers configured to store memory addresses of data blocks requested from the memory circuit in most recent memory read transactions;
a plurality of write address registers configured to store memory addresses of data blocks written to the memory circuit in most recent memory write transactions;
a plurality of data registers configured to selectively store, based on a mode count, the data blocks requested from the memory circuit in the most recent memory read transactions and the data blocks written to the memory circuit in the most recent memory write transactions; and
a control circuit configured to:
receive a first memory read transaction requesting a first data block at a first memory address;
generate a hit signal in an active state in response to determining that the first data block is stored in the plurality of data registers;
return the first data block from the plurality of data registers in response to the hit signal; and
adjust the mode count based on

Assignees

• Qualcomm Inc

Inventors

• Shrimal Saurabh Kumar
• Dager Sandeep
• Kumar Ravindra
• Pandey Sahil

Classifications

• G06F2212/502

  using adaptive policy · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title