System and method for scheduling operations in a graphics pipeline

Patent metadata

Field	Value
Publication number	US-12436767-B2
Application number	US-202218066115-A
Country	US
Kind code	B2
Filing date	Dec 14, 2022
Priority date	Dec 14, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Systems, apparatuses, and methods for implementing a hierarchical scheduling in fixed-function graphics pipeline are disclosed. In various implementations, a processor includes a pipeline comprising a plurality of fixed-function units and a scheduler. The scheduler is configured to schedule a first operation for execution by one or more fixed-function units of the pipeline by scheduling the first operation with a first unit of the pipeline, responsive to a first mode of operation and schedule a second operation for execution by a selected fixed-function unit of the pipeline by scheduling the second operation directly to the selected fixed-function unit, independent of a sequential arrangement of the one or more fixed-function units in the pipeline, responsive to a second mode of operation.

First claim

What is claimed is:

1. A processor comprising:
a pipeline comprising one or more fixed-function units comprising circuitry; and
an output buffer corresponding to the pipeline and configured to store data received from an end of the pipeline; and
a scheduler comprising circuitry configured to:
receive a first operation to be executed by a first fixed-function unit of the pipeline;
cause the first operation to be executed, and generate an output, by the first fixed-function unit;
retrieve the output from the output buffer, responsive to a first mode of operation; and
retrieve the output from the first fixed-function unit instead of the output buffer, responsive to a second mode of operation.

2. The processor as recited in claim 1 , further comprising control circuitry configured to:
receive, from the scheduler in an input buffer corresponding to the first fixed-function unit, data for scheduling the first operation;
transmit the received data to the first fixed-function unit.

3. The processor as recited in claim 2 , wherein the control circuitry is further configured to store the output from the first fixed-function unit in an output buffer corresponding to the first fixed-function unit, responsive to the second mode of operation.

4. The processor as recited in claim 3 , wherein the control circuitry is further configured to convey the stored output from the output buffer corresponding to the first fixed-function unit to an input buffer corresponding to a second fixed-function unit to schedule a second operation for the second fixed-function unit.

5. The processor as recited in claim 3 , wherein the control circuitry is configured to convey data pertaining to the output from the output buffer corresponding to the first fixed-function unit to a memory location, responsive to the second mode of operation.

6. The processor as recited in claim 5 , wherein the memory location is one of a memory subsystem associated with the processor, and a mailbox accessible by the scheduler.

7. The processor as recited in claim 1 , wherein the first fixed-function unit is configured to send a notification to the scheduler, responsive to the second mode of operation, the notification at least in part indicative of completion of execution of the first operation at the first fixed-function unit.

8. A method comprising:
receiving, by a scheduler comprising circuitry, a first operation to be executed by circuitry of a first fixed-function unit of a graphics pipeline;
causing, by the scheduler, the first operation to be executed, and generate an output, by the first fixed-function unit;
retrieving, by the scheduler responsive to a first mode of operation, the output from an output buffer corresponding to the graphics pipeline and configured to store data received from an end of the graphics pipeline; and
retrieving, by the scheduler, the output from the first fixed-function unit instead of the output buffer, responsive to a second mode of operation.

9. The method as recited in claim 8 , further comprising:
receiving, by control circuitry in an input buffer corresponding to the first fixed-function unit, data for scheduling the first operation to the first-fixed function unit; and
transmitting, by the control circuitry, the received data to the first fixed-function unit.

10. The method as recited in claim 9 , further comprising storing, by the control circuitry, the output from the first fixed-function unit in an output buffer corresponding to the first-fixed function unit, responsive to the second mode of operation.

11. The method as recited in claim 9 , further comprising conveying, by the control circuitry, the stored output from the output buffer corresponding to the first fixed-function unit to an input buffer corresponding to a second fixed-function unit to schedule a second operation for the second fixed-function unit.

12. The method as recited in claim 10 , further comprising, conveying, by the control circuitry, data pertaining to the output from the output buffer corresponding to the first fixed-function unit to a memory location.

13. The method as recited in claim 12 , wherein the memory location is one of a memory subsystem, and a mailbox accessible by the scheduler.

14. The method as recited in claim 9 , further comprising, receiving, by the scheduler, a notification from the first fixed-function unit, responsive to the second mode of operation, the notification at least in part indicative of completion of execution of the first operation.

15. A computing system comprising:
a central processing unit comprising circuitry;
a graphics processing unit comprising circuitry, the graphics processing unit comprising:
a pipeline comprising one or more fixed-function units, each comprising circuitry; and
a scheduler comprising circuitry configured to:
receive a first operation to be executed by a first fixed-function unit of the pipeline;
cause the first operation to be executed, and generate an output, by the first fixed-function unit;
retrieve, responsive to a first mode of operation, the output from an output buffer corresponding to the pipeline, and configured to store data received from an end of the pipeline; and
retrieve the output from the first fixed-function unit instead of the output buffer, responsive to a second mode of operation.

16. The computing system as recited in claim 15 , further comprising control circuitry configured to:
receive, from the scheduler in an input buffer corresponding to the first fixed-function unit, data for scheduling the first operation;
transmit the received data to the first fixed-function unit.

17. The computing system as recited in claim 16 , wherein the control circuitry is further configured to store the output from the first fixed-function unit in an output buffer corresponding to the first-fixed function unit, responsive to the second mode of operation.

18. The computing system as recited in claim 17 , wherein the control circuitry is further configured to convey the stored output from the output buffer corresponding to the first fixed-function unit to an input buffer corresponding to a second fixed-function unit to schedule a second operation for the second fixed-function unit.

19. The computing system as recited in claim 17 , wherein the control circuitry is configured to convey data pertaining to the output from the output buffer corresponding to the first fixed-function unit to a memory location, responsive to the second mode of operation.

20. The computing system as recited in claim 19 , wherein the memory location is one of a memory subsystem, and a mailbox accessible by the scheduler.

Assignees

• Advanced Micro Devices Inc

Inventors

• Chajdas Matthäus G
• Mantor Michael J
• Mccrary Rex Eldon
• Brennan Christopher J
• Martin Robert
• Bennett Brian Kenneth

Classifications

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F9/5055

  considering software capabilities, i.e. software resources associated or available to the machine · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/3873

  Variable length pipelines, e.g. elastic pipeline · CPC title