Memory system using host memory buffer and operation method thereof

Patent metadata

Field	Value
Publication number	US-12436713-B2
Application number	US-202418662090-A
Country	US
Kind code	B2
Filing date	May 13, 2024
Priority date	Nov 10, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

There is provided an operation method of a memory system which includes a host and a storage device, and the operation method includes allocating a portion of a host memory included in the host for a host memory buffer to be used by a controller of the storage device, setting a set feature command such that the host memory buffer is enabled, setting a retention command including information about a response speed of the host memory buffer, selecting an operation mode of the host memory buffer, based on the retention command, and selecting one of a plurality of power states, which the controller supports, based on a performance objective of the operation mode of the host memory buffer.

First claim

What is claimed is:

1. An operation method of a storage device which shares a portion of a host memory of a host as a host memory buffer, the method comprising:
receiving a command to enable the host memory buffer;
receiving information about a response speed of the host memory buffer; and
operating the host memory buffer based on the response speed of the host memory buffer,
wherein the information about the response speed of the host memory buffer comprising a first response speed level, among a plurality of response speed levels, and
wherein the operating the host memory buffer based on the response speed of the host memory buffer comprises controlling the host memory buffer to operate in a first mode, among a plurality of modes, based on the first response speed level.

2. The method of claim 1 , further comprising:
receiving at least a portion of data present in the host memory buffer to be stored in the storage device.

3. The method of claim 2 , further comprising:
preventing a controller of the storage device from accessing the host memory buffer after the receiving of the at least the portion of the data present in the host memory buffer is completed.

4. The method of claim 2 , further comprising:
performing background operation after the receiving of the at least the portion of the data present in the host memory buffer is completed.

5. The method of claim 1 , further comprising:
preventing a controller of the storage device from accessing the host memory buffer in response to the response speed of the host memory buffer.

6. The method of claim 1 , further comprising:
receiving information about a power state, among a plurality of power states supported by a controller of the storage device.

7. The method of claim 6 , further comprising:
receiving at least a portion of data present in the host memory buffer after the receiving of the information about the power state.

8. The method of claim 7 , further comprising:
preventing the controller from accessing the host memory buffer after the after the receiving of the at least the portion of the data present in the host memory buffer.

9. The method of claim 7 , further comprising:
performing an operation permitted in the received power state after the after the receiving of the at least the portion of the data present in the host memory buffer.

10. The method of claim 1 , further comprising:
receiving a retention recovery command from the host; and
sending data present in the storage device to the host for updating contents in the host memory buffer.

11. The method of claim 1 , wherein the information about the response speed of the host memory buffer comprises an address and a retention level of the host memory buffer, and
wherein the retention level is determined by comparing an expected response speed of the host memory buffer and at least one reference response time.

12. The method of claim 11 , further comprising:
selecting an operation mode of the host memory buffer based on the retention level.

13. An operation method of a storage device, the method comprising:
receiving an enable host memory command to share a portion of a host memory of a host as a host memory buffer;
receiving a retention command comprising information about a response speed of the host memory buffer, the information about the response speed of the host memory buffer comprising a first response speed level, among a plurality of response speed levels; and
selecting a first mode, among a plurality of modes, of operation of the host memory buffer, based on the retention command corresponding to the first response speed level.

14. The method of claim 13 , further comprising:
receiving at least a portion of data present in the host memory buffer to be stored in the storage device.

15. The method of claim 14 , further comprising:
preventing a controller of the storage device from accessing the host memory buffer after the receiving of the at least the portion of the data present in the host memory buffer is completed.

16. The method of claim 13 , further comprising:
preventing a controller of the storage device from accessing the host memory buffer in response to the response speed of the host memory buffer.

17. A storage device which shares a host memory of a host as a host memory buffer, comprising:
a nonvolatile memory device storing data; and
a storage controller configured to control the nonvolatile memory device,
wherein the storage controller is further configured to:
receive information about a response speed of the host memory buffer, and
operate the host memory buffer, based on the response speed of the host memory,

wherein the information about the response speed of the host memory buffer comprising a first response speed level, among a plurality of response speed levels, and
wherein the operating the host memory buffer based on the response speed of the host memory buffer comprises controlling the host memory buffer to operate in a first mode, among a plurality of modes, based on the first response speed level.

18. The storage device of claim 17 , wherein the storage controller is further configured to receive at least a portion of data present in the host memory buffer to be stored in the storage device.

19. The storage device of claim 18 , wherein the storage controller is further configured to be blocked from accessing the host memory buffer after receiving of the at least the portion of the data present in the host memory buffer is completed.

20. The storage device of claim 17 , wherein the storage controller is further configured to be blocked from accessing the host memory buffer in response to the response speed of the host memory buffer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Bumhee
• Kim Wooram
• Kim Hyunseok
• Park Kihyun
• Lee Sooyun
• Cho Hyeongyu
• Choi Shin-Ho

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0622

  in relation to access · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title