Method and device of accessing memory with near memory accelerator

Patent metadata

Field	Value
Publication number	US-12436679-B2
Application number	US-202418439092-A
Country	US
Kind code	B2
Filing date	Feb 12, 2024
Priority date	Feb 13, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Disclosed are a method of accessing a memory and an electronic device for performing the method. The electronic device includes a processor, and a memory electrically connected to the processor, wherein the processor may be configured to select a rank including bank groups of the memory, select a bank corresponding to a memory address to be accessed from among banks included in the selected rank, select a row and one or more columns from rows and columns of the selected bank corresponding to the memory address, and generate the memory address to access the memory based on an address mapping scheme according to the selected rank, the selected bank, the selected row, and the selected one or more columns.

First claim

What is claimed is:

1. An electronic device comprising:
a processor; and
a memory electrically connected to the processor,
wherein the processor is configured to:
select, between a first rank and a second rank, a rank comprising bank groups of the memory,
select a bank corresponding to a memory address to be accessed from among banks included in the selected rank,
select a row and one or more columns from among rows and columns of the selected bank, and
generate the memory address to access the memory based on an address mapping scheme according to the selected rank, the selected bank, the selected row, and the selected one or more columns, wherein when the first rank is selected, reshuffling of an order of the generated address is prevented, and wherein when the second rank is selected, reshuffling of the order of the generated address is not prevented.

2. The electronic device of claim 1 , wherein
the processor is further configured to select a channel to access a near memory accelerator (NMA) included in the memory, the channel selected from among channels connected to the memory.

3. The electronic device of claim 1 , wherein
the processor is further configured to generate a column identity corresponding to the selected one or more columns, and wherein
a width of the column identity is greater than a width of a set byte offset, and the column identity is set such that it is not to be repeated within a set wrap around window.

4. The electronic device of claim 1 , wherein
the selected row corresponds to a row hit for all write addresses.

5. The electronic device of claim 1 , wherein
the processor is further configured to select banks from different bank groups among the bank groups included in the selected rank.

6. A method of accessing a memory, the method comprising:
selecting, between a first rank and a second rank, a rank comprising bank groups of a memory;
selecting a bank corresponding to a memory address to be accessed, the bank selected from among banks included in the selected rank;
selecting a row and one or more columns from rows and columns of the selected bank; and
generating the memory address to access the memory based on an address mapping scheme according to the selected rank, the selected bank, the selected row, and the selected one or more columns, wherein when the first rank is selected, reshuffling of an order of generated addresses, including the generated address, is prevented, and wherein when the second rank is selected, reshuffling of the order of the generated addresses is not prevented.

7. The method of claim 6 , further comprising:
selecting a channel to access a near memory accelerator (NMA) included in the memory, from among channels connected to the memory.

8. The method of claim 6 , further comprising:
generating a column identity corresponding to the selected one or more columns, wherein
a width of the column identity is greater than a width of a set byte offset, and the column identity is set not to be repeated within a set wrap around window.

9. The method of claim 6 , wherein
the selected row corresponds to a row hit for all write addresses.

10. The method of claim 6 , wherein
the selecting of the bank comprises selecting banks from different bank groups among the bank groups included in the selected rank.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Roy Arnab
• Das Saptarsi
• Chandrasekharan Kiran Kolar
• Cho Yeongon

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0629 Primary

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title