Hybrid clocking scheme for SERDES physical layer circuits

Patent metadata

Field	Value
Publication number	US-12436558-B2
Application number	US-202318509643-A
Country	US
Kind code	B2
Filing date	Nov 15, 2023
Priority date	Nov 15, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A first inverter in a clock generation circuit is coupled to an input clock signal and has multiple driver slices. Each driver slice includes first transistors that have gates coupled to the input clock signal, second transistors that have sources coupled to rails of a power supply. Each of the second transistors has a drain coupled to a source of one of the first transistors. The second transistors are turned on or turned off based on signaling state of a differential enable signal. A tuning resistor is coupled to the drains of the first transistors and further coupled to an output of the first inverter. A second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.

First claim

What is claimed is:

1. A clock generation circuit, comprising:
a first inverter coupled to an input clock signal and comprising driver slices, each driver slice in the first inverter comprising:
a first pair of transistors that have gates that are coupled to the input clock signal;
a second pair of transistors that includes a first transistor that has a source coupled to a higher voltage rail of a power supply and a drain coupled to a source of a first transistor in the first pair of transistors, and a second transistor that has a source coupled to a lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the first pair of transistors, wherein the second pair of transistors is turned on when a first differential enable signal is in a first signaling state and turned off when the first differential enable signal is in a second signaling state; and
a first tuning resistor coupled to the drains of the first pair of transistors and further coupled to an output of the first inverter;

a first tunable capacitor coupled to the output of the first inverter; and
a second inverter that has an input coupled to the output of the first inverter and that outputs a quadrature version of the input clock signal, wherein the second inverter comprises
a third pair of transistors that have gates that are coupled to the output of the first inverter;
a fourth pair of transistors that includes a first transistor that has a source coupled to the higher voltage rail of the power supply and a drain coupled to a source of a first transistor in the third pair of transistors, and a second transistor that has a source coupled to the lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the third pair of transistors, wherein the fourth pair of transistors is turned on when a second differential enable signal is in the first signaling state and turned off when the second differential enable signal is in the second signaling state;
a second tuning resistor coupled to the drains of the third pair of transistors and to an output of the second inverter; and
a second tunable capacitor coupled to the output of the second inverter.

2. The clock generation circuit of claim 1 , wherein the first tunable capacitor and the first tuning resistor in each turned-on driver slice in the first inverter are configured as a resistance-capacitance (RC) circuit.

3. The clock generation circuit of claim 1 , wherein the first tunable capacitor comprises:
a plurality of switches controlled by a first multibit select signal; and
a plurality of capacitors, each capacitor being configured to be coupled between the output of the first inverter and a voltage rail of the power supply when a corresponding switch in the plurality of switches is turned on.

4. The clock generation circuit of claim 1 , wherein the second tunable capacitor comprises:
one or more switches controlled by a second multibit select signal; and
one or more capacitors, each of the one or more capacitors being configured to be coupled between the output of the second inverter and a voltage rail of the power supply when a corresponding switch in the one or more switches is turned on.

5. The clock generation circuit of claim 1 , further comprising:
a second tuning resistor that couples the input of the second inverter to the output of the first inverter; and
a second tunable capacitor coupled to the input of the second inverter.

6. A clock generation circuit, comprising:
a first inverter coupled to an input clock signal and comprising driver slices, each driver slice in the first inverter comprising:
a first pair of transistors that have gates that are coupled to the input clock signal;
a second pair of transistors that includes a first transistor that has a source coupled to a higher voltage rail of a power supply and a drain coupled to a source of a first transistor in the first pair of transistors, and a second transistor that has a source coupled to a lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the first pair of transistors, wherein the second pair of transistors is turned on when a first differential enable signal is in a first signaling state and turned off when the first differential enable signal is in a second signaling state; and
a first tuning resistor coupled to the drains of the first pair of transistors and further coupled to an output of the first inverter;

a second inverter that has an input coupled to the output of the first inverter and that outputs a quadrature version of the input clock signal;
a first tunable capacitor coupled to the output of the first inverter;
a second tuning resistor that couples the input of the second inverter to the output of the first inverter; and
a second tunable capacitor coupled to the input of the second inverter, wherein the second tunable capacitor comprises:
one or more switches controlled by a second multibit select signal; and
one or more capacitors, each of the one or more capacitors being configured to be coupled between the input of the second inverter and a voltage rail of the power supply when a corresponding switch in the one or more switches is turned on.

7. A clock generation circuit, comprising:
a first inverter coupled to an input clock signal and comprising driver slices, each driver slice in the first inverter comprising:
a first pair of transistors that have gates that are coupled to the input clock signal;
a second pair of transistors that includes a first transistor that has a source coupled to a higher voltage rail of a power supply and a drain coupled to a source of a first transistor in the first pair of transistors, and a second transistor that has a source coupled to a lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the first pair of transistors, wherein the second pair of transistors is turned on when a first differential enable signal is in a first signaling state and turned off when the first differential enable signal is in a second signaling state; and
a first tuning resistor coupled to the drains of the first pair of transistors and further coupled to an output of the first inverter;

a second inverter that has an input coupled to the output of the first inverter and that outputs a quadrature version of the input clock signal;
a first tunable capacitor coupled to the output of the first inverter;
a second tunable capacitor coupled to the input of the second inverter; and
a second tuning resistor that couples the input of the second inverter to the output of the first inverter, wherein the second tuning resistor comprises:
at least one switch controlled by a third select signal; and
at least one resistor coupled between the output of the first inverter and the input of the second inverter, the at least one resistor being coupled in parallel with another resistor when the at least one switch is turned on.

8. The clock generation circuit of claim 5 , wherein the second tuning resistor has a fixed resistance value.

9. The clock generation circuit of claim 6 , wherein the second tuning resistor has a fixed resistance value.

Assignees

• Qualcomm Inc

Inventors

• Saputra Nitz
• Wadhwa Sameer

Classifications

• H03K5/15006

  with two programmable outputs · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/134

  with field-effect transistors · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title