Display panel and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12433102-B2
Application number	US-202117621250-A
Country	US
Kind code	B2
Filing date	Nov 24, 2021
Priority date	Nov 17, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

The present application discloses a display panel and a manufacturing method thereof. The display panel includes a substrate, a first gate, a first gate insulating layer, an active layer, an interlayer dielectric layer, a first via, a second via, a source, and a drain; the active layer is disposed on the substrate, the active layer includes at least a first sub-active layer and a second sub-active layer stacked, the second sub-active layer is disposed on a side of the first sub-active layer away from the substrate, and a number of gallium atoms in the first sub-active layer is greater than a number of gallium atoms in the second sub-active layer.

First claim

What is claimed is:

1. A display panel, wherein the display panel comprises:
a substrate;
a first gate, wherein the first gate is disposed on the substrate;
a first gate insulating layer, wherein the first gate insulating layer is disposed on the substrate and covers the first gate;
an active layer, wherein the active layer is disposed on the first gate insulating layer, the active layer comprises at least a first sub-active layer, and a second sub-active layer and a third sub-active layer that are stacked, the first sub-active layer is disposed on the first gate insulating layer, the second sub-active layer is disposed on the first sub-active layer, and the third sub-active layer is disposed on the second sub-active layer; a material of the first sub-active layer comprises indium gallium zinc oxide, wherein a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the first sub-active layer is indium:gallium:zinc=M:1:N, wherein 0<M<1, 0<N<1; a material of the second sub-active layer comprises indium gallium zinc oxide, wherein a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the second sub-active layer is indium:gallium:zinc=1:1:1;
an interlayer dielectric layer disposed on the first gate insulating layer and covering the active layer;
a first via, wherein the first via penetrates at least the interlayer dielectric layer;
a second via, wherein the second via penetrates at least the interlayer dielectric layer;
a source, wherein the source is disposed on the interlayer dielectric layer and electrically connected to the active layer through the first via;
a drain, wherein the drain is disposed on the interlayer dielectric layer and electrically connected to the active layer through the second via;
a second gate insulating layer, wherein the second gate insulating layer is disposed on the active layer;
a second gate, wherein the second gate is disposed on the second gate insulating layer;
a third via, wherein the third via penetrates the interlayer dielectric layer;
a fourth via, wherein the fourth via penetrates the interlayer dielectric layer and the first gate insulating layer; and
a connection electrode, wherein the connection electrode is disposed in the third via and the fourth via for connecting the first gate and the second gate.

2. The display panel according to claim 1 , wherein a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the third sub-active layer is indium:gallium:zinc=X:1:Y, 0<X<1, 0<Y<1.

3. The display panel according to claim 2 , wherein the first sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer, and the third sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer.

4. The display panel according to claim 1 , wherein a thickness of the first sub-active layer and a thickness of the third sub-active layer are less than or equal to 15 nm, and a thickness of the second sub-active layer ranges from 10 nm to 90 nm.

5. The display panel according to claim 2 , wherein the number of gallium atoms in the third sub-active layer is equal to the number of gallium atoms in the first sub-active layer.

6. The display panel according to claim 1 , wherein the display panel further comprises:
a passivation layer, wherein the passivation layer is disposed on the interlayer dielectric layer;
a contact electrode, wherein the contact electrode is disposed on the passivation layer, one end of the contact electrode is connected to the drain;
a planarization layer, wherein the planarization layer is disposed on the passivation layer;
an anode disposed on the planarization layer, wherein another end of the contact electrode is connected to the anode;
a pixel definition layer, wherein the pixel definition layer is disposed on the planarization layer and covers a portion of the anode;
a light-emitting layer, wherein the light-emitting layer is disposed within an opening of the pixel definition layer; and
a cathode, wherein the cathode is disposed on the light-emitting layer.

7. A display panel, wherein the display panel comprises:
a substrate;
a first gate, wherein the first gate is disposed on the substrate;
a first gate insulating layer, wherein the first gate insulating layer is disposed on the substrate and covers the first gate;
an active layer comprising at least a first sub-active layer and a second sub-active layer that are stacked, the first sub-active layer is disposed on the first gate insulating layer, and the second sub-active layer is disposed on the first sub-active layer; a material of the first sub-active layer comprises indium gallium zinc oxide, wherein a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the first sub-active layer is indium:gallium:zinc=M:1:N, wherein 0<M<1, 0<N<1; a material of the second sub-active layer comprises indium gallium zinc oxide, wherein a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the second sub-active layer is indium:gallium:zinc=1:1:1;
an interlayer dielectric layer disposed on the first gate insulating layer and covering the active layer;
a first via, wherein the first via penetrates at least the interlayer dielectric layer;
a second via, wherein the second via penetrates at least the interlayer dielectric layer;
a source, wherein the source is disposed on the interlayer dielectric layer and electrically connected to the active layer through the first via;
a drain, wherein the drain is disposed on the interlayer dielectric layer and electrically connected to the active layer through the second via;
a passivation layer, wherein the passivation layer is disposed on the interlayer dielectric layer;
a contact electrode, wherein the contact electrode is disposed on the passivation layer, one end of the contact electrode is connected to the drain;
a planarization layer, wherein the planarization layer is disposed on the passivation layer;
an anode disposed on the planarization layer, wherein another end of the contact electrode is connected to the anode;
a pixel definition layer, wherein the pixel definition layer is disposed on the planarization layer and covers a portion of the anode;
a light-emitting layer, wherein the light-emitting layer is disposed within an opening of the pixel definition layer; and
a cathode, wherein the cathode is disposed on the light-emitting layer.

8. The display panel according to claim 7 , wherein the active layer further comprises:
a third sub-active layer, wherein the third sub-active layer is disposed on the second sub-active layer, a ratio of a number of indium atoms, a number of gallium atoms, and a number of zinc atoms in the third sub-active layer is indium:gallium:zinc=X:1:Y, 0<X<1, 0<Y<1.

9. The display panel according to claim 8 , wherein the first sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer, and the third sub-active layer comprises a nitrogen-doped indium gallium zinc oxide active layer.

10. The display panel according to claim 7 , wherein the display panel further comprises:
a second gate insulating layer, wherein the second gate insulating layer is disposed on the active layer;
a second gate, wherein the second gate is disposed on the second gate insulating layer;
a third via, wherein the third via penetrates the interlayer dielectric layer;
a fourth via, wherein the fourth via penetrates the interlayer dielectric layer and the first gate insulating layer; and
a connection electrode, wherein the connection electrode is disposed in the third via and the fourth via for connec

Assignees

• Huizhou China Star Optoelectronics Display Co Ltd
• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Hu Kai

Classifications

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title