Display panel and display apparatus including the same

US12433099B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12433099-B2
Application numberUS-202318102571-A
CountryUS
Kind codeB2
Filing dateJan 27, 2023
Priority dateMay 12, 2022
Publication dateSep 30, 2025
Grant dateSep 30, 2025

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel includes a first display area having a plurality of first display elements, a second display area having a plurality of second display elements, and a third display area between the first display area and the second display area, wherein the third display area includes a first sub display area adjacent to the second display area in a first direction, and a second sub display area adjacent to the second display area in a second direction, the first sub display area comprises a bypass area, some data lines pass across the first sub display area and the second sub display area, and change their extension direction in the bypass area.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel comprising: a substrate comprising a first display area in which a plurality of first display elements are disposed, a second display area in which a plurality of second display elements are disposed, and a third display area between the first display area and the second display area; a plurality of first pixel circuits in the first display area and connected to the plurality of first display elements; a plurality of second pixel circuits in the third display area and connected to the plurality of second display elements; and a plurality of first data lines connected to the plurality of first pixel circuits of the first display area and the plurality of second pixel circuits of the third display area, wherein the third display area comprises a first sub display area adjacent to the second display area in a first direction, and a second sub display area adjacent to the second display area in a second direction, the first sub display area comprises a bypass area, and the plurality of first data lines pass across the first sub display area and the second sub display area, and an extension direction thereof changes in the bypass area. 2. The display panel of claim 1 , wherein the bypass area extends along the first sub display area in the second direction, and is adjacent to the second sub display area and the second display area. 3. The display panel of claim 1 , further comprising: a plurality of third display elements and a plurality of third pixel circuits connected to the plurality of third display elements, arranged in the first sub display area of the third display area; a plurality of fourth display elements and a plurality of fourth pixel circuits connected to the plurality of fourth display elements, arranged in the second sub display area of the third display area; and a plurality of second data lines connected to the first pixel circuits of the first display area and the fourth pixel circuits of the second sub display area, and of which an extension direction changes in the bypass area of the first sub display area. 4. The display panel of claim 3 , wherein each of the first data lines and the second data lines is connected to the first pixel circuits and the third pixel circuits of the first sub display area, arranged in a same column. 5. The display panel of claim 3 , wherein a size of the third pixel circuits in the first direction is less than a size of the first pixel circuits in the first direction. 6. The display panel of claim 5 , wherein each of the third display elements overlaps a portion of each of the third pixel circuits to which the third display element is connected and a portion of the bypass area. 7. The display panel of claim 6 , wherein one of the first data line and the second data line crossing each other in the bypass area comprises a first portion in the first sub display area and a second portion in the second sub display area, and the first portion is electrically connected to the second portion in the bypass area. 8. The display panel of claim 3 , wherein at least one of the first data lines and at least one of the second data lines cross each other in the bypass area. 9. The display panel of claim 8 , wherein a portion of each of the first data lines and a portion of each of the second data lines that cross each other in the bypass area are on different layers from each other. 10. The display panel of claim 9 , wherein, regarding one of the first data line and the second data line crossing each other in the bypass area, a portion in the first sub display area and a portion in the second sub display area are electrically connected to each other. 11. The display panel of claim 9 , wherein one of the first data line and the second data line crossing each other in the bypass area comprises a first portion in the first sub display area, a second portion in the second sub display area, and a third portion arranged in the bypass area and connecting the first portion and the second portion. 12. A display panel comprising: a substrate comprising a first display area in which a plurality of first display elements are disposed, a second display area in which a plurality of second display elements are disposed, and a third display area between the first display area and the second display area; a plurality of first pixel circuits in the first display area and connected to the plurality of first display elements; a plurality of second pixel circuits in the third display area and connected to the plurality of second display elements; and a plurality of first data lines connected to the plurality of first pixel circuits of the first display area and the plurality of second pixel circuits of the third display area, wherein the third display area comprises a pair of first sub display areas spaced apart from each other in a first direction with the second display area therebetween, and a pair of second sub display areas spaced apart from each other in a second direction with the second display area therebetween, each of the pair of first sub display areas comprises a bypass area, and the first data lines pass across one of the first sub display areas and the second sub display areas, and an extension direction thereof changes in the bypass area. 13. The display panel of claim 12 , further comprising: a plurality of third display elements and a plurality of third pixel circuits connected to the third display elements, in the first sub display areas of the third display area; a plurality of fourth display elements and a plurality of fourth pixel circuits connected to the fourth display elements, in the second sub display areas of the third display area; and a plurality of second data lines which are connected to the first pixel circuits of the first display area and the fourth pixel circuits of each of the second sub display areas, and of which an extension direction changes in the bypass area of each of the first sub display areas, wherein each of the first data lines and the second data lines are connected to the first pixel circuits and the third pixel circuits of the first sub display area, in a same column. 14. The display panel of claim 13 , wherein a size of the third pixel circuits in the first direction is less than a size of the first pixel circuits in the first direction. 15. The display panel of claim 13 , wherein at least one of the first data lines and at least one of the second data lines cross each other in the bypass area. 16. The display panel of claim 13 , wherein a portion of each of the first data lines and a portion of each of the second data lines, which cross each other in the bypass area, are on different layers from each other. 17. The display panel of claim 13 , wherein one of the first data line and the second data line crossing each other in the bypass area comprises a first portion and a second portion in each of the pair of first sub display areas, and a connection portion in the second sub display area, and the first portion and the second portion are electrically connected to each other by the connection portion in the bypass area. 18. The display panel of claim 13 , wherein one of the first data line and the second data line crossing each other in the bypass area comprises a first portion and a second portion in each of the pair of first sub display areas, a third portion in the second sub display area, and a first connection portion and a second connection portion in the bypass area of each of the pair of first sub display areas, and the first connect

Assignees

Inventors

Classifications

  • OLEDs integrated with inorganic image sensors · CPC title

  • Power management, e.g. power saving · CPC title

  • Layout of electrodes and connections · CPC title

  • Aspects of interface with display user · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

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Frequently asked questions

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What does patent US12433099B2 cover?
A display panel includes a first display area having a plurality of first display elements, a second display area having a plurality of second display elements, and a third display area between the first display area and the second display area, wherein the third display area includes a first sub display area adjacent to the second display area in a first direction, and a second sub display are…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).