Circuit module and method for manufacturing the same
US-2020008301-A1 · Jan 2, 2020 · US
Module and method for manufacturing same
US12432858B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12432858-B2 |
| Application number | US-202217934328-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 22, 2022 |
| Priority date | Mar 27, 2020 |
| Publication date | Sep 30, 2025 |
| Grant date | Sep 30, 2025 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
A module includes a substrate having a first surface and at least one recess on the first surface, and an electronic component mounted on the first surface. The electronic component is connected to the substrate via a plurality of bumps. All of the plurality of bumps are connected to the first surface inside any of the at least one recess. A height of the plurality of bumps is greater than a depth of the at least one recess. When viewed in a direction perpendicular to the first surface, a part of the electronic component is located outside an outer periphery of any recess selected from the at least one recess.
First claim
Opening claim text (preview).
The invention claimed is: 1. A module comprising: a substrate having a first surface and at least one recess on the first surface; and an electronic component mounted on the first surface, wherein the electronic component is connected to the substrate via a plurality of bumps, all of the plurality of bumps are connected to the first surface inside any of the at least one recess, a height of each of the plurality of bumps is greater than a depth of the at least one recess, a part of the electronic component is located outside an outer periphery of any recess selected from the at least one recess when viewed in a direction perpendicular to the first surface, and two or more bumps selected from the plurality of bumps are connected to the first surface in one recess selected from the at least one recess. 2. The module according to claim 1 , further comprising: a sealing resin disposed so as to cover the electronic component; and a shield film covering the sealing resin and further covering a side surface of the substrate. 3. The module according to claim 1 , wherein the substrate has a second surface as a surface opposite from the first surface, and another electronic component different from the electronic component is mounted on the second surface. 4. The module according to claim 1 , wherein a distance between an outline of the electronic component and an outline of the recess in the part, where the outline of the electronic component is located outside the outline of the recess, is 20 μm or more and 500 μm or less. 5. The module according to claim 4 , wherein a distance between an outline of the electronic component and an outline of the recess in the part, where the outline of the electronic component is located outside the outline of the recess, is 30 μm or more and 80 μm or less.
Assignees
Inventors
Classifications
the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title
Package configurations · CPC title
protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title
for connecting multiple chips together · CPC title
comprising multiple insulating layers · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12432858B2 cover?
- A module includes a substrate having a first surface and at least one recess on the first surface, and an electronic component mounted on the first surface. The electronic component is connected to the substrate via a plurality of bumps. All of the plurality of bumps are connected to the first surface inside any of the at least one recess. A height of the plurality of bumps is greater than a de…
- Who is the assignee on this patent?
- Murata Manufacturing Co
- What technology area does this patent fall under?
- Primary CPC classification H05K1/183. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).