Multiplexer and serializer including the same

Patent metadata

Field	Value
Publication number	US-12431997-B2
Application number	US-202217680787-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Jul 5, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

First claim

What is claimed is:

1. A multiplexer that selects one of a first to a fourth data signal in response to a first to a fourth pulse, the first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle, the multiplexer comprising:
a NAND gate configured to output a first gate signal in response to receiving the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse;
a NOR gate configured to output a second gate signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse;
a first transistor including a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected with an output terminal of the multiplexer; and
a second transistor including a first terminal connected with the output terminal of the multiplexer, a gate that receives the second gate signal, and a second terminal to which a ground voltage is applied, wherein:
the first data signal corresponds to a rising edge of the first pulse, and
the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

2. The multiplexer of claim 1 , wherein the NAND gate includes:
a third transistor including a first terminal to which a second power supply voltage is applied, a gate to which the first pulse is applied, and a second terminal connected with the gate of the first transistor;
a fourth transistor including a first terminal to which a third power supply voltage is applied, a gate to which the first data signal is applied, and a second terminal connected with the gate of the first transistor;
a fifth transistor including a first terminal connected with the gate of the first transistor, a gate to which the first pulse is applied, and a second terminal connected with a first node;
a sixth transistor including a first terminal connected with the first node, a gate to which the first data signal is applied, and a second first node to which the ground voltage is applied; and
a seventh transistor including a first terminal connected with the first node, a gate to which the fourth complementary data signal is applied, and a second terminal to which the ground voltage is applied.

3. The multiplexer of claim 2 , wherein the NAND gate further includes an eighth transistor including a first terminal to which a fourth power supply voltage is applied, a gate to which the first data signal is applied, and a second terminal connected with the first node.

4. The multiplexer of claim 3 , wherein the seventh transistor is implemented with an NMOS transistor and the eighth transistor is implemented with a PMOS transistor.

5. The multiplexer of claim 1 , wherein the NOR gate includes:
a third transistor including a first terminal to which a second power supply voltage is applied, a gate to which the first data signal is applied, and a second terminal connected with a first node;
a fourth transistor including a first terminal connected with the first node, a gate to which the first complementary pulse is applied, and a second terminal connected with the gate of the second transistor;
a fifth transistor including a first terminal connected with the gate of the second transistor, a gate to which the first complementary pulse is applied, and a second terminal to which the ground voltage is applied;
a sixth transistor including a first terminal connected with the gate of the second transistor, a gate to which the first data signal is applied, and a second terminal to which the ground voltage is applied; and
a seventh transistor including a first terminal to which a third power supply voltage is applied, a gate to which the fourth complementary data signal is applied, and a second terminal connected with the first node.

6. The multiplexer of claim 5 , wherein the NOR gate further includes an eighth transistor including a first terminal connected with the first node, a gate to which the first data signal is applied, and a second terminal to which the ground voltage is applied.

7. The multiplexer of claim 6 , wherein the seventh transistor is implemented with a PMOS transistor and the eighth transistor is implemented with an NMOS transistor.

8. A serializer comprising:
a clock multiplexer configured to generate first to fourth pulses based on first to fourth clocks, wherein the first to fourth clocks have a phase difference of 90 degrees with each other and the first to fourth pulses toggle sequentially; and
a multiplexer configured to output an output signal, which is based on a first to a fourth data signal, in response to the first to fourth pulses and first to fourth complementary pulses respectively complementary to the first to fourth pulses, wherein:
the first to fourth data signals correspond to the first to fourth pulses, respectively,
the multiplexer includes:
a NAND gate configured to output a first gate signal in response to receiving the first data signal, a fourth complementary data signal complementary to the fourth data signal, and the first pulse; and
a NOR gate configured to output a second gate signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse, and

a level of the output signal is based on the first gate signal and the second gate signal.

9. The serializer of claim 8 , wherein:
the NAND gate includes a first transistor including a first terminal to which the first gate signal is applied, a gate to which the first pulse is applied, and a second terminal connected with a first node, and
a level of a voltage of the first node falls in response to the fourth complementary data signal having a first logical value at a first rising edge of the fourth pulse.

10. The serializer of claim 9 , wherein:
at a second rising edge of the first pulse following the first rising edge of the fourth pulse, the voltage of the first node is transferred to the first terminal of the first transistor, to which the first gate signal is applied, in response to the first data signal having a second logical value, and
the first logical value and the second logical value are different.

11. The serializer of claim 9 , wherein at a second rising edge of the first pulse following the first rising edge of the fourth pulse, the level of the voltage of the first node rises in response to the first data signal having the first logical value.

12. The serializer of claim 8 , wherein:
the NOR gate includes a first transistor including a first terminal connected with a first node, a gate to which the first complementary pulse is applied, and a second terminal to which the second gate signal is applied, and
a level of a voltage of the first node falls in response to the fourth complementary data signal having a first logical value at a first rising edge of the fourth pulse.

13. The serializer of claim 12 , wherein:
at a second rising edge of the first pulse following the first rising edge of the fourth pulse, the voltage of the first node is transferred to the first terminal of the first transistor, to which the second gate signal is applied, in response to the first data signal having a second logical value, and
the first logical value and the second logical value are different.

14. The serializer of claim 12 , wherein at a second rising edge of the first pulse following the first rising edge of the fourth pulse, the level of the voltage of the first node falls in response to the fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Jaehyeok
• Kwon Daehyun
• Kim Saetbyeol
• Kim Hye-Ran

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title

• H03K17/005

  with several inputs only · CPC title

• H03K19/018507

  Interface arrangements · CPC title