Analog multiplier accumulator with unit element gain balancing

Patent metadata

Field	Value
Publication number	US-12430100-B2
Application number	US-202117335206-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Jun 1, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values, and a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. The X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

First claim

We claim:

1. A Gain Balanced Analog Multiplier Accumulator (AMAC) comprising:
a differential charge transfer bus;
an inference memory storing a plurality of X input values and W coefficient values;
a Multiply-Accumulate (MAC) controller coupled to the inference memory to output a subset of the X input values and associated W coefficient values;
a plurality of MAC unit elements (MAC UEs) performing multiply-accumulate operations on the X input and the W input of the subset of the X input values and associated W coefficient values during conversion cycles, each MAC UE having an X input and a W input with individual bits coupled to respective logic gates, each logic gate performing a bitwise multiplication as a logic gate output, each logic gate output coupled through a respective binary-weighted capacitor to the differential charge transfer bus, thereby transferring a binary weighted charge to the differential charge transfer bus corresponding to a weighted multiplication result on each conversion cycle, each MAC UE having an associated gain error;
the MAC controller addressing the inference memory to arrange the subset of the X input values and associated W coefficient values to a different MAC UE of the plurality of MAC UEs for subsequent multiplication operations, thereby reducing a gain error contributed by a particular MAC UE;
and wherein each logic gate is a NAND gate having an X binary input and a W binary input, and each bit of the X binary input and each bit of the W binary input are applied to a respective NAND gate, the respective NAND gate having an output and a complement output, each output and complement output coupled to the differential charge transfer bus through capacitors with relative weights of 1, 2, 4, 2, 4, 8, 4, 8, and 16.

2. The Gain Balanced AMAC of claim 1 where the arrangement of the subset of the X input values and associated W coefficient values to a different MAC UE of the plurality of MAC UEs is a round robin arrangement.

3. The Gain Balanced AMAC of claim 1 where the arrangement of the subset of the X input values and associated W coefficient values to the plurality of MAC UEs is configured to reduce a MAC UE gain error contribution from one or more MAC UEs.

4. The Gain Balanced AMAC of claim 1 where the binary weighted charge is transferred to the differential charge transfer bus according to a bit position of the X input and the W coefficient input.

5. The Gain Balanced AMAC of claim 1 where the X input and the W input of each MAC UE are each three bits.

6. The Gain Balanced AMAC of claim 1 where each logic gate performs an AND or a NAND operation on each X input and each W input.

7. The Gain Balanced AMAC of claim 1 where the plurality of MAC UEs is more than 100.

8. The Gain Balanced AMAC of claim 1 where at least one subset of the inference memory comprises a plurality of X input values and a single W coefficient value.

9. The Gain Balanced AMAC of claim 1 where the W coefficient of the W coefficient values includes a sign bit.

10. The Gain Balanced AMAC of claim 9 where each associated W coefficient includes a sign bit and each MAC UE comprises a positive MAC UE enabled when the sign bit is positive and a negative MAC UE enabled with the sign bit is negative.

11. The Gain Balanced AMAC of claim 1 where the differential charge transfer bus is coupled to a programmable charge bias.

12. The Gain Balanced AMAC of claim 1 where the differential charge transfer bus is coupled to an analog to digital converter.

13. A Gain Balanced Analog Multiplier-Accumulator (AMAC) comprising:
a MAC controller coupled to an inference memory;
the inference memory storing a plurality of X input values, each X input value having an associated W coefficient, the inference memory outputting a subset of X input values and associated W coefficient values in a plurality of Multiply-Accumulate (MAC) cycles;
a plurality of Analog Multiply Accumulate Unit Elements (AMAC UEs), each AMAC UE having an X input and a W input, the X input and W input coupled to a plurality of NAND gates to perform bit-wise multiplication and coupling the bit-wise multiplication result as respective charge through a charge transfer capacitor to a differential charge transfer bus on each MAC cycle, the differential charge transfer bus comprising a positive charge transfer bus and a negative charge transfer bus;
the MAC controller configured to cause the inference memory to output each subset of X input values and associated W coefficient values in equal number to the plurality of AMAC UEs;
on each MAC cycle, the inference memory directing an output comprising an X input value of the subset of X input values and associated W coefficient value to a different AMAC UE of the plurality of MAC UEs than for a preceding MAC cycle;
the differential charge transfer bus thereby providing a multiply-accumulate value from preceding MAC cycles.

14. The Gain Balanced AMAC of claim 13 where outputting the subset of X input values and associated W coefficient values to different AMAC UEs than for a preceding MAC cycle is circular round robin.

15. The Gain Balanced AMAC of claim 14 where the circular round robin is the inference memory outputting each subsequent X input value and associated W coefficient to an adjacent AMAC UE from a previous MAC cycle.

16. The Gain Balanced AMAC of claim 14 where the charge transfer bus is coupled to an Analog to Digital Converter generating a digital output.

17. The Gain Balanced AMAC of claim 14 where each AMAC UE has a register for storage of the X input and W input values from the inference memory.

18. A Gain Balanced AMAC comprising:
an inference memory containing subsets of inference data, each subset of inference data comprising a plurality of X input values and a W coefficient;
a MAC controller coupled to the inference memory;
a plurality of Multiply-Accumulate Unit Elements (MAC UEs) in equal number to a number of the subsets of inference data, each MAC UE comprising NAND or AND gates receiving an X input value of the plurality of X input values and a W coefficient from the inference memory and generating a multiplication result as an analog charge coupled through a respective capacitor from a respective NAND or AND gate to an analog charge bus on each conversion cycle command;
the inference memory outputting each subset of inference data to different MAC UEs on subsequent conversion cycle commands;
and where the analog charge comprises a positive charge coupled to a positive charge bus and a negative charge coupled to a negative charge bus.

19. The Gain Balanced AMAC of claim 18 where the inference memory outputting each subset of inference data to different MAC UEs on subsequent conversion cycle commands is a round robin output.

20. The Gain Balanced AMAC of claim 18 where the inference memory mixes coefficient sets of an X input value and respective W coefficient value to different MAC UEs in a non-sequential manner.

21. A Gain Balanced Analog Multiplier Accumulator (AMAC) comprising:
a differential charge transfer bus;
an inference memory storing a plurality of X input values and W coefficient values;
a Multiply-Accumulate (MAC) controller coupled to the inference memory to output a subset of the X input values and associated W coefficient values;
a plurality of MAC unit elements (MAC UEs) performing multiply-accumulate operations on the X input and the W input of the subset of the X input values and associated W coefficient values during conversion cycles

Assignees

• Redpine Signals Inc
• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• G06F7/523

  Multiplying only · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• H03M1/804

  with charge redistribution · CPC title