Flexible organic light emitting display device and method of manufacturing the same

US12429969B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12429969-B2
Application numberUS-202418663704-A
CountryUS
Kind codeB2
Filing dateMay 14, 2024
Priority dateJul 10, 2017
Publication dateSep 30, 2025
Grant dateSep 30, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An OLED device includes a substrate having a display region including a pixel region and first and second peripheral regions surrounding the pixel region. A bending region is between the display region and the second peripheral region. A buffer layer has a first opening exposing an upper surface of the substrate. A plurality of pixel structures is disposed in the pixel region on the buffer layer. An insulation layer structure is disposed on the buffer layer. The insulation layer structure has a second opening exposing an upper surface of the substrate that is disposed in the bending region and a first portion of the buffer layer that is disposed adjacent to the bending region. A fan-out wiring is disposed between two adjacent insulation layers of the plurality of insulation layers. The fan-out wiring is disposed in the first peripheral region and/or the second peripheral region.

First claim

Opening claim text (preview).

What is claimed is: 1. An organic light emitting display (OLED) device, comprising: a substrate having a display region, a first peripheral region, a second peripheral region that is spaced apart from the first peripheral region, and a bending region that is interposed between the first peripheral region and the second peripheral region; a buffer layer disposed on the substrate, the buffer layer having a first removed region exposing a portion of an upper surface of the substrate, the first removed region overlapping at least a portion of the bending region; a pixel structure disposed in the display region on the buffer layer and including a lower electrode, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer; a semiconductor element electrically connected to the pixel structure and disposed in the display region between the pixel structure and the buffer layer; an insulation layer structure including a plurality of insulation layers disposed on the buffer layer, the insulation layer structure having a second removed region exposing the first removed region and a top surface of a portion of the buffer layer that is disposed adjacent to the first removed region; a fan-out wiring disposed in the insulation layer structure without forming a step of a top surface of the insulation layer structure, the fan-out wiring including a first fan-out wiring disposed in the first peripheral region and a second fan-out wiring disposed in the second peripheral region; a first planarization layer disposed in the display region, the first peripheral region disposed adjacent to the bending region, the bending region, and the second peripheral region disposed adjacent to the bending region on the substrate, the first planarization layer filling the first removed region and the second removed region; and a connection electrode disposed on the first planarization layer, the connection electrode being electrically connected between the first fan-out wiring and the second fan-out wiring. 2. The OLED device of claim 1 , wherein the first removed region further overlaps at least one of a portion of the first peripheral region and a portion of the second peripheral region. 3. The OLED device of claim 1 , wherein a size of the second removed region is greater than the size of the first removed region. 4. The OLED device of claim 1 , wherein the first fan-out wiring is electrically connected to the pixel structure, the second fan-out wiring is electrically connected to an external device, and the connection electrode electrically connects the pixel structure to the external device via the first fan-out wiring and the second fan-out wiring. 5. The OLED device of claim 4 , wherein the connection electrode includes first through (N)th connection electrodes, where N is an integer greater than 1, and the first through (N)th connection electrodes are spaced apart from each other by a predetermined distance along a second direction that is perpendicular to a first direction extending from the display region into the second peripheral region. 6. The OLED device of claim 1 , further comprising a second planarization layer covering the connection electrode and the first planarization layer. 7. The OLED device of claim 6 , wherein the first planarization layer and the second planarization layer are interposed between the pixel structure and the semiconductor element in the display region. 8. The OLED device of claim 7 , wherein the semiconductor element includes: an active layer disposed on the buffer layer; a gate electrode disposed on the active layer; and source and drain electrode disposed on the insulation layer structure. 9. The OLED device of claim 8 , wherein the gate electrode and the fan-out wiring are concurrently formed using a same material. 10. The OLED device of claim 8 , further comprising a connection pattern disposed in the display region and configured to electrically connect the lower electrode of the pixel structure to the drain electrode of the semiconductor element. 11. The OLED device of claim 10 , wherein the connection pattern and the connection electrode are concurrently formed using a same material. 12. The OLED device of claim 8 , further comprising a conductive pattern configured to electrically connect the connection electrode to the fan-out wiring, at least a portion of the conductive pattern being disposed inside a contact hole formed via the insulation layer structure. 13. The OLED device of claim 12 , wherein the conductive pattern and the source and drain electrodes are concurrently formed using a same material. 14. The OLED device of claim 12 , wherein the insulation layer structure includes a first contact hole disposed in the first peripheral region and a second contact hole disposed in the second peripheral region, and the conductive pattern includes a first conductive pattern at least a portion of which is filled in the first contact hole and a second conductive pattern at least a portion of which is filled in the second contact hole. 15. An electronic device, comprising: a signal generating device configured to generate a plurality of driving signals; and an organic light emitting display (OLED) device configured to display an image based on the driving signals, wherein the OLED device includes: a substrate having a display region, a first peripheral region, a second peripheral region that is spaced apart from the first peripheral region, and a bending region that is interposed between the first peripheral region and the second peripheral region; a buffer layer disposed on the substrate, the buffer layer having a first removed region exposing a portion of an upper surface of the substrate, the first removed region overlapping at least a portion of the bending region; a pixel structure disposed in the display region on the buffer layer and including a lower electrode, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer; a semiconductor element electrically connected to the pixel structure and disposed in the display region between the pixel structure and the buffer layer; an insulation layer structure including a plurality of insulation layers disposed on the buffer layer, the insulation layer structure having a second removed region exposing the first removed region and a top surface of a portion of the buffer layer that is disposed adjacent to the first removed region; a fan-out wiring disposed in the insulation layer structure without forming a step of a top surface of the insulation layer structure, the fan-out wiring including a first fan-out wiring disposed in the first peripheral region and a second fan-out wiring disposed in the second peripheral region; a first planarization layer disposed in the display region, the first peripheral region disposed adjacent to the bending region, the bending region, and the second peripheral region disposed adjacent to the bending region on the substrate, the first planarization layer filling the first removed region and the second removed region; and a connection electrode disposed on the first planarization layer, the connection electrode being electrically connected between the first fan-out wiring and the second fan-out wiring, and wherein the first fan-out wiring is electrically connected to the pixel structure, the second fan-out wiring is electrically connected to the signal generating device, and the connection electrode electrically connects the pixel structure to the signal generating device via the first fan-out wiring an

Assignees

Inventors

Classifications

  • Pixel-defining structures or layers, e.g. banks · CPC title

  • Flexible substrates · CPC title

  • Interconnections, e.g. wiring lines or terminals · CPC title

  • Electrodes · CPC title

  • Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

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Frequently asked questions

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What does patent US12429969B2 cover?
An OLED device includes a substrate having a display region including a pixel region and first and second peripheral regions surrounding the pixel region. A bending region is between the display region and the second peripheral region. A buffer layer has a first opening exposing an upper surface of the substrate. A plurality of pixel structures is disposed in the pixel region on the buffer laye…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).