Manufacturing method of array substrate, array substrate, and display panel

Patent metadata

Field	Value
Publication number	US-12426418-B2
Application number	US-202217772772-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Apr 8, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

The present application provides a manufacturing method of an array substrate, an array substrate, and a display panel. The manufacturing method of the array substrate includes providing a base substrate; forming a conductive layer and a photoresist layer on the base substrate; patterning the photoresist layer and the conductive layer to form a conductive area and an electroplating area electrically connected to each other; removing the photoresist layer; forming an electroplating layer; and disconnecting the electroplating area from the conductive area. In the present application, the photoresist layer has a less thickness to reduce manufacturing costs of the array substrate.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, wherein the manufacturing method comprises following steps:
providing a base substrate;
sequentially forming a conductive layer and a photoresist layer on the base substrate;
patterning the photoresist layer and the conductive layer, wherein the patterned conductive layer comprises a conductive area and an electroplating area which are electrically connected;
removing the photoresist layer;
forming an electroplating layer on the conductive layer at a position corresponding to the electroplating area; and
disconnecting the electroplating area from the conductive area.

2. The manufacturing method of the array substrate according to claim 1 , wherein the step of patterning the photoresist layer and the conductive layer comprises:
patterning the photoresist layer to expose a portion of the conductive layer; and
patterning the conductive layer and removing the exposed portion of the conductive layer to form a conductive electrode, a plurality of connection portions, a plurality of trace portions, and a plurality of seed portions, wherein the conductive electrode and the connection portions form a conductive area, the trace portions and the seed portions form an electroplating area, each trace portion is electrically connected to the seed portions, and the connection portions are connected between the conductive electrode and the trace portions, so that the electroplating area and the conductive area are electrically connected to each other.

3. The manufacturing method of the array substrate according to claim 2 , wherein the conductive layer comprises multiple trace portions and multiple connection portions, and the connection portions and the trace portions are connected in a one-to-one correspondence.

4. The manufacturing method of the array substrate according to claim 3 , wherein the conductive electrode is strip-shaped, the trace portions are arranged side by side along an extending direction of the conductive electrode, and each connection portion is connected between the conductive electrode and one of the trace portions.

5. The manufacturing method of the array substrate according to claim 4 , wherein along the extending direction of the conductive electrode, a width of each connection portion is less than a width of the correspondingly connected trace portion.

6. The manufacturing method of the array substrate according to claim 2 , wherein the step of forming the electroplating layer on the conductive layer at a position corresponding to the electroplating area comprises:
providing an electrolytic cell, wherein the electrolytic cell comprises an anode, a cathode, and an electrolyte electrically connected between the anode and the cathode;
placing the trace portions and the seed portions in the electrolyte of the electrolytic cell;
electrically connecting the conductive electrode to the cathode of the electrolytic cell; and
applying a preset current between the anode and the cathode of the electrolytic cell, so that the electroplating layer is formed on the trace portions and the seed portions.

7. The manufacturing method of the array substrate according to claim 2 , wherein the step of disconnecting the electroplating area from the conductive area comprises:
removing and cutting off the connection portions, so that the conductive electrode is disconnected from the trace portions, and the electroplating area is disconnected from the conductive area.

8. The manufacturing method of the array substrate according to claim 2 , wherein the manufacturing method further comprises following steps:
patterning the trace portions and the electroplating layer on the trace portions to form a plurality of conductive lines, so that the conductive lines are electrically connected to the seed portions.

9. The manufacturing method of the array substrate according to claim 1 , wherein a thickness of the photoresist layer is greater than or equal to 1 micrometer and less than or equal to 1.5 micrometers.

10. An array substrate, comprising:
a base substrate;
a conductive layer disposed on the base substrate, wherein the conductive layer comprises a conductive area and an electroplating area both in a patterned form, and the conductive area and the electroplating area are spaced apart; and
an electroplating layer disposed on the conductive layer at a position corresponding to the electroplating area,
wherein the conductive area comprises a conductive electrode, the electroplating area comprises a plurality of trace portions and a plurality of seed portions, the trace portions are electrically connected to the seed portions, and the electroplating layer is disposed on the trace portions and the seed portions.

11. The array substrate according to claim 10 , wherein the electroplating area comprises multiple trace portions and multiple seed portions, and each of the trace portions is electrically connected to the seed portions.

12. The array substrate according to claim 11 , wherein the seed portions and the electroplating layer on the seed portions form one or more of a gate, a gate line, a source-drain, or a data line.

13. The array substrate according to claim 11 , wherein the trace portions and the electroplating layer on the trace portions constitute a plurality of conductive lines, and the conductive lines are electrically connected to the seed portions.

14. The array substrate according to claim 13 , wherein the seed portions are distributed in an array, and each of the conductive lines is electrically connected to each column of the seed portions.

15. The array substrate according to claim 11 , wherein the conductive electrode is strip-shaped, and the trace portions are arranged side by side along an extending direction of the conductive electrode.

16. The array substrate according to claim 15 , wherein the conductive electrode is disposed at an edge of the base substrate, and the trace portions are arranged side by side on a same side of the conductive electrode.

17. The array substrate according to claim 10 , wherein a thickness of the conductive layer is greater than or equal to 0.5 micrometer and less than or equal to 0.6 micrometer; and a thickness of the electroplating layer is greater than or equal to 6 micrometers.

18. The array substrate according to claim 10 , wherein a material of the conductive layer is same as a material of the electroplating layer.

19. A display panel, comprising:
the array substrate of claim 10 ;
a light-emitting device disposed on the array substrate;
an encapsulating assembly disposed on the light-emitting device.

20. An array substrate, comprising:
a base substrate;
a conductive layer disposed on the base substrate, wherein the conductive layer comprises a conductive area and an electroplating area both in a patterned form, and the conductive area and the electroplating area are spaced apart; and
an electroplating layer disposed on the conductive layer at a position corresponding to the electroplating area,
wherein the conductive area comprises a conductive electrode, the electroplating area comprises multiple trace portions and multiple seed portions, and each of the trace portions is electrically connected to the seed portions, and the electroplating layer is disposed on the trace portions and the seed portions.

Assignees

• Tcl China Star Optoelectronics Tech Co Ltd

Inventors

• Zhao Bin
• Xiao Juncheng
• Lin Xiaodan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H20/032

  of electrodes · CPC title