Structures of sram cell and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-12426231-B2
Application number	US-202318366471-A
Country	US
Kind code	B2
Filing date	Aug 7, 2023
Priority date	Aug 7, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the first direction; and a fourth n-channel layer engaged with a fourth gate layer to form a sixth device, the fourth gate layer coupled to a second word line and the fourth n-channel layer coupled to the third n-channel layer along the second direction.

First claim

What is claimed is:

1. A static random-access memory (SRAM) cell, comprising:
a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device;
a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction;
a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction;
a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction;
a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the first direction; and
a fourth n-channel layer engaged with a fourth gate layer to form a sixth device, the fourth gate layer coupled to a second word line and the fourth n-channel layer coupled to the third n-channel layer along the second direction.

2. The SRAM cell of claim 1 , wherein each of the first, second, third, and fourth n-channel layers includes at least one material selected from the group consisting of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), indium gallium arsenide (InGaAs), carbon nanotube (CNT), transition metal dichalcogenides (TMD), and black phosphorus nanoribbon (BPNR).

3. The SRAM cell of claim 1 , wherein each of the first and second p-channel layers includes at least one material selected from the group consisting of nickel oxide (NiO), copper oxide (Cu 2 O), copper aluminum oxide (CuAlO 2 ), copper gallium oxide (CuGaO 2 ), copper indium oxide (CuInO 2 ), strontium copper oxide (SrCu 2 O 2 ), tin oxide (SnO), and combinations thereof.

4. The SRAM cell of claim 1 , wherein the first device and the second device form a first cross-coupled inverter, and wherein the fourth device and the fifth device form a second cross-coupled inverter.

5. The SRAM cell of claim 1 , further comprising a gate dielectric layer between each of the first, second, third, and fourth n-channel layers and each of the first, second, third, and fourth gate layers, respectively, and between each of the first and second p-channel layers and each of the first and the second gate layers, respectively.

6. The SRAM cell of claim 1 , wherein the first n-channel layer is coupled to the second n-channel layer by a first interconnect structure along the second direction and the third n-channel layer is coupled to the fourth n-channel layer by a second interconnect structure along the second direction.

7. The SRAM cell of claim 6 , wherein the first interconnect structure extends along the third direction to be further coupled to the third gate layer and the second interconnect structure extends along the third direction to be further coupled to the first gate layer.

8. The SRAM cell of claim 6 , further comprising a fifth n-channel layer engaged with a fifth gate layer to form a seventh device and a sixth n-channel layer engaged with a sixth gate layer to form an eighth device adjacent the seventh device along the second direction, the sixth gate layer coupled to a read word line, wherein the second interconnect structure extends along the third direction to be further coupled to the fifth gate layer.

9. The SRAM cell of claim 1 , wherein the first p-channel layer is leveled with the second p-channel layer along the first direction.

10. The SRAM cell of claim 1 , wherein the first p-channel layer is leveled with the third n-channel layer along the first direction.

11. A static random-access memory (SRAM) cell, comprising:
a first n-type metal-oxide-semiconductor (NMOS) device including a first channel layer engaged with a first gate layer;
a first p-type metal-oxide-semiconductor (PMOS) device including a second channel layer engaged with the first gate layer, wherein the first gate layer is interposed between the first channel layer and the second channel layer along a first direction, and wherein the first NMOS device and the first PMOS device form a first inverter;
a second NMOS device adjacent the first NMOS device along a second direction perpendicular to the first direction and including a third channel layer engaged with a second gate layer;
a third NMOS device including a fourth channel layer engaged with a third gate layer, the fourth channel layer spaced from the third channel layer along a third direction perpendicular to the first direction and the second direction;
a second PMOS device including a fifth channel layer engaged with the third gate layer, wherein the third gate layer is interposed between the fourth channel layer and the fifth channel layer along the first direction, and wherein the third NMOS device and the second PMOS device form a second inverter; and
a fourth NMOS device adjacent the third NMOS device along the second direction and including a sixth channel layer engaged with a fourth gate layer.

12. The SRAM cell of claim 11 , wherein:
the second gate layer is coupled to a first word line;
the fourth gate layer is coupled to a second word line;
a source/drain of the first PMOS device and a source/drain of the second PMOS device are each coupled to a reference voltage; and
a source/drain of the first NMOS device and a source/drain of the third NMOS device are each coupled to ground.

13. The SRAM cell of claim 11 , wherein each of the first, third, fourth, and sixth channel layers includes at least one material selected from the group consisting of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), indium gallium arsenide (InGaAs), carbon nanotube (CNT), transition metal dichalcogenides (TMD), black phosphorus nanoribbon (BPNR), and combinations thereof.

14. The SRAM cell of claim 11 , wherein each of the second and fifth channel layers includes at least one material selected from the group consisting of nickel oxide (NiO), copper oxide (Cu 2 O), copper aluminum oxide (CuAlO 2 ), copper gallium oxide (CuGaO 2 ), copper indium oxide (CuInO 2 ), strontium copper oxide (SrCu 2 O 2 ), tin oxide (SnO), and combinations thereof.

15. The SRAM cell of claim 11 , wherein the second channel layer is leveled with a top the fifth channel layer along the first direction.

16. The SRAM cell of claim 11 , wherein the second channel layer is leveled with the fourth channel layer along the first direction.

17. The SRAM cell of claim 11 , further comprising:
a first interconnect structure configured to couple the first NMOS device, the first PMOS device, and the second NMOS device to the third gate layer; and
a second interconnect structure configured to couple the third NMOS device, the second PMOS device, and the fourth NMOS device to the first gate layer.

18. A method of forming a memory cell, comprising:
providing a semiconductor substrate including a plurality of devices;
forming a first dielectric layer over the semiconductor substrate;
forming a first channel layer and a second channel layer in the first dielectric layer, the first channel layer and the second channel layer having the same conductivity type;
forming a first contact adjacent the first channel layer and a vertical p

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Kuan-Chung
• Chen wei-hua
• Lee Chieh
• Lee Chun-Ying
• Liu Yi-Ching
• Huang Chia-En

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title

• H10B10/125

  the MOSFET being a thin film transistor [TFT] · CPC title