Image in-painting for irregular holes using partial convolutions

Patent metadata

Field	Value
Publication number	US-12425605-B2
Application number	US-201916360895-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 21, 2018
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A neural network architecture is disclosed for performing image in-painting using partial convolution operations. The neural network processes an image and a corresponding mask that identifies holes in the image utilizing partial convolution operations, where the mask is used by the partial convolution operation to zero out coefficients of the convolution kernel corresponding to invalid pixel data for the holes. The mask is updated after each partial convolution operation is performed in an encoder section of the neural network. In one embodiment, the neural network is implemented using an encoder-decoder framework with skip links to forward representations of the features at different sections of the encoder to corresponding sections of the decoder.

First claim

What is claimed is:

1. A computer-implemented method comprising:
performing, using a neural network, two or more successive partial convolutions using corresponding masks to generate two or more feature maps that successively increase a number of valid pixels used in each respective partial convolution to at least partially fill one or more holes in one or more images.

2. The method of claim 1 , further comprising updating at least one of the corresponding masks subsequent to performing each of the two or more successive of the partial convolutions.

3. The method of claim 2 , wherein updating the at least one of the corresponding masks comprises performing a convolution operation on the at least one of the corresponding masks and normalizing a result of the convolution operation.

4. The method of claim 1 , wherein the at least one of the two or more successive partial convolutions uses an encoder section and a decoder section, and wherein each stage of the decoder section is connected to an input of a corresponding stage of the encoder section via a skip link.

5. The method of claim 4 , wherein each stage of the decoder section comprises an up-sampling layer, a concatenation layer, and a partial convolution layer, and wherein the concatenation layer combines an output of the up-sampling layer with the input of the corresponding stage of the encoder section from the skip link.

6. The method of claim 1 , further comprising training one or more neural networks to perform the at least one of the two or more successive partial convolutions based, at least in part, on a total loss function comprising a weighted sum of loss components, to adjust attributes of the one or more neural networks.

7. The method of claim 6 , further comprising using two or more neural network layers to perform the successive one or more partial convolutions to cause the one or more holes in the one or more images to be filled based, at least in part, on one or more non-hole regions of the one or more images at each of the two or more neural network layers.

8. A system, comprising:
a memory storing one or more images; and
at least one parallel processing unit coupled to the memory and comprising circuitry to perform, using a neural network, two or more successive partial convolutions using corresponding masks to generate two or more feature maps that successively increase a number of valid pixels used in each respective partial convolution to at least partially fill one or more holes in one or more images.

9. The system of claim 8 , wherein the circuitry is to update at least one of the corresponding masks subsequent to performing one or more of the partial convolutions.

10. The system of claim 8 , wherein at least one of the two or more successive partial convolutions uses an encoder section and a decoder section, and wherein each stage of the decoder section is connected to an input of a corresponding stage of the encoder section via a skip link.

11. The system of claim 10 , wherein each stage of the decoder section comprises an up-sampling layer, a concatenation layer, and a partial convolution layer, and wherein the concatenation layer combines an output of the up-sampling layer with the input of the corresponding stage of the encoder section from the skip link.

12. The system of claim 10 , wherein each stage of the encoder section comprises a partial convolution layer configured to apply a convolution kernel to an image of the one or more images in the input, wherein, for each pixel of at least one of the two or more feature maps generated by the partial convolution layer, coefficients in the convolution kernel have been masked by a portion of the mask corresponding to the pixel.

13. The system of claim 12 , wherein the partial convolution layer is configured to use a stride greater than one to reduce a resolution of at least one feature map of the two or more feature maps compared to a resolution of an input to the partial convolution layer.

14. The system of claim 8 , wherein the circuitry is further to automatically update at least one of the corresponding masks for each layer of the neural network.

15. One or more processors, A processor comprising:
circuitry to;
perform, using a neural network, two or more successive partial convolutions using corresponding masks to generate two or more feature maps that successively increase a number of valid pixels used in each respective partial convolution to at least partially fill one or more holes in one or more images.

16. The one or more processors of claim 15 , wherein at least one of the two or more successive partial convolutions uses an encoder and a decoder, and wherein each stage of the decoder is connected to an input of a corresponding stage of the encoder via a skip link.

17. The one or more processors of claim 15 , wherein at least one of the two or more successive partial convolutions uses a decoder, and wherein each stage of the decoder comprises an up-sampling layer, a concatenation layer, and a partial convolution layer, and wherein the concatenation layer combines an output of an upsampling layer with an input of the corresponding stage of an encoder from a skip link.

18. The one or more processors of claim 15 , wherein one or more partial convolution layers provide results to a Leaky Rectified Linear Unit (Leaky ReLU).

19. The one or more processors of claim 15 , wherein at least one of the two or more successive partial convolutions uses an encoder, wherein each stage of the encoder comprises a partial convolution layer to apply a convolution kernel to at least one of the one or more images in an input, wherein, of each pixel of at least one feature map of the two or more feature maps generated by the partial convolution layer, coefficients in the convolution kernel are masked by a portion of the mask corresponding to the pixel.

20. The one or more processors of claim 15 , wherein one or more partial convolution layers are to use a stride greater than one to reduce a resolution of at least one feature map of the two or more feature maps compared to a resolution of an input to the partial convolution layer.

Assignees

• Nvidia Corp

Inventors

• Liu Guilin
• Reda Fitsum A
• Shih Kevin
• Wang Ting-Chun
• Tao Andrew
• Catanzaro Bryan

Classifications

• G06N3/0455

  Auto-encoder networks; Encoder-decoder networks · CPC title

• G06T5/77 Primary

  Retouching; Inpainting; Scratch removal · CPC title

• G06T2207/20084

  Artificial neural networks [ANN] · CPC title

• G06T2207/20081

  Training; Learning · CPC title

• G06T5/20

  using local operators · CPC title