Communication device and communication system

Patent metadata

Field	Value
Publication number	US-12425495-B2
Application number	US-202418663657-A
Country	US
Kind code	B2
Filing date	May 14, 2024
Priority date	Jun 22, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Communication devices and systems are disclosed. In one example, a communication device includes a LINK that performs protocol conversion of a signal from a Master and outputs the converted signal to a Slave SerDes, and of a signal from the Slave SerDes and outputs the converted signal to the Master. The LINK alternatively selects a first mode and a second mode. In the first mode, the LINK converts a 1-byte signal transmitted from the Master into a signal of a first communication standard in units of the 1-byte signal and transmits the converted signal to the Slave SerDes, then receives a signal of the first communication standard including an ACK signal representing an acknowledgement or a NACK signal representing a negative acknowledgement, and converts the received signal into a signal of a second communication standard and transmits the converted signal to the Master.

First claim

The invention claimed is:

1. A communication apparatus, comprising:
a memory storing instructions, and
a processor configured to execute the instructions to perform operations comprising:
performing protocol-conversion on a signal from a Master and outputting a converted signal to a Slave Serializer/Deserializer (SerDes) and performing protocol-conversion on a signal from the Slave SerDes and outputting the converted signal to the Master;
alternatively selecting a first mode and a second mode for transmitting the signal from the Master to the Slave SerDes:
in the first mode, repeating processing of converting the signal transmitted from the Master into a signal of a first communication standard in units of one byte, receiving a signal of the first communication standard including one of an acknowledgement (ACK) signal representing an affirmative response and a non-acknowledgement (NACK) signal representing a negative response after transmitting the converted signal to the Slave SerDes, converting the received signal into a signal of a second communication standard, and transmitting the converted signal to the Master;
in the second mode, transmitting, to the Master, a signal including one of the ACK signal and the NACK signal every time a signal of a plurality of bytes transmitted from the Master is received byte by byte, collectively transmitting the converted signal to the Slave SerDes after a conversion of the signal of a plurality of bytes received from the Master is completed, then, receiving a signal of the first communication standard including one of the ACK signal and the NACK signal from the Slave SerDes and holding the received signal, and then, converting, in response to a read request from the Master, the signal of the first communication standard into a signal of the second communication standard and transmitting the converted signal to the Master, wherein
a signal to be transmitted to the Slave SerDes includes command information indicating content transmitted from the Master, and
a signal to be transmitted to the Master includes command information indicating content transmitted from the Slave SerDes.

2. The communication apparatus according to claim 1 , wherein a number of bytes of the signal to be transmitted to the Slave SerDes in the first mode is one of 2 bytes and 3 bytes except for clock frequency information and error correction code.

3. The communication apparatus according to claim 1 , wherein the operations further comprise:
in the first mode,
transitioning to a first state upon receiving a signal including a Start Condition from the Master, converts, when transitioning to the first state, the Start Condition into a signal of the first communication standard and transmitting an obtained signal to the Slave SerDes;
then, transitioning to a second state upon receiving, in the first state, a signal including address information of a final destination apparatus of one byte from the Master, and holding a clock from the Master at a low level;
converting, in the second state, a signal including the address information into a signal of the first communication standard and transmitting the obtained signal to the Slave SerDes;
then, upon receiving, in the second state, a signal including one of the ACK signal and the NACK signal from the Slave SerDes, recognizing, where a specific bit of the signal including the address information has a first bit value, the specific bit as writing and transitions to a third state; and
converting, in the third state, the signal including one of the ACK signal and the NACK signal received from the Slave SerDes into a signal of the second communication standard, transmitting the obtained signal to the Master, and then, releasing the holding of the low level of the clock from the Master.

4. The communication apparatus according to claim 3 , wherein the operations further comprise:
in the first mode,
transitioning to a fourth state upon receiving, in the third state, a signal including writing data of one byte from the Master;
converting, in the fourth state, the received signal into a signal of the first communication standard, and transmitting the obtained signal to the Slave SerDes; and
then, upon receiving, in the fourth state, a signal including one of the ACK signal and the NACK signal from the Slave SerDes, converting the received signal into a signal of the second communication standard and transmitting the obtained signal to the Master.

5. The communication apparatus according to claim 4 , wherein the operations further comprise:
in the first mode,
transitioning to a fifth state where the signal including one of the ACK signal and the NACK signal is not received from the Slave SerDes within a predetermined time period in one of the second state and the fourth state; and
performing error processing in the fifth state.

6. The communication apparatus according to claim 1 , wherein the operations further comprise:
in the first mode,
transitioning to a first state upon receiving a signal including one of a Start Condition and a ReStart Condition from the Master;
converting, when transitioning to the first state, the signal including one of the Start Condition and the ReStart Condition into a signal of the first communication standard and transmitting an obtained signal to the Slave SerDes;
then, transitioning to a second state upon receiving, in the first state, a signal including address information of a final destination apparatus of one byte from the Master, and holding a clock from the Master at a low level;
converting, in the second state, a signal including the address information into a signal of the first communication standard and transmitting the obtained signal to the Slave SerDes;
then, upon receiving, in the second state, a signal including one of the ACK signal and the NACK signal from the Slave SerDes, recognizing, where a specific bit of the signal including the address information has a second bit value, the specific bit as reading and transition to a sixth state; and
converting, in the sixth state, the signal including one of the ACK signal and the NACK signal received from the Slave SerDes into a signal of the second communication standard, transmitting the obtained signal to the Master, and then, releasing the holding of the low level of the clock from the Master.

7. The communication apparatus according to claim 6 , wherein the operations further comprise:
in the first mode,
transitioning to a seventh state upon receiving, in the sixth state, a signal including reading data of one byte from the Slave SerDes;
converting, in the seventh state, the received signal into a signal of the second communication standard, and transmitting the obtained signal to the Master; and
then, transitioning to the sixth state upon receiving, in the seventh state, a signal including one of the ACK signal and the NACK signal from the Master, converting the received signal into a signal of the first communication standard, and transmitting the obtained signal to the Slave SerDes.

8. The communication apparatus according to claim 7 , wherein the operations further comprise:
in the first mode,
transitioning to an eighth state where the reading data is not received from the Slave SerDes within a predetermined time period in the sixth state;
transitioning to the eighth state where the one of the ACK signal and the NACK signal is not received from the Master within the predetermined time period in the seventh state; and
performing error processing in the eighth state to avoid deadlock of an entire system including the communication apparatus, the Master, and the Slave SerDes.

9. The communication apparatus according to claim 1 , wherein the operations

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Yamada Junya
• Ota Satoshi
• Hyakudai Toshihisa

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L1/1607 Primary

  Details of the supervisory signal · CPC title

• H04L69/08 Primary

  Protocols for interworking; Protocol conversion · CPC title