Data transmission method, processor system, and memory access system

Patent metadata

Field	Value
Publication number	US-12425268-B2
Application number	US-202218146720-A
Country	US
Kind code	B2
Filing date	Dec 27, 2022
Priority date	Jun 28, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Example data transmission methods, processor systems, and memory access systems are provided. One example processor system is applied to a source end device. The processor system includes a processor core and a first remote direct memory access (RDMA) network interface card. The processor core is configured to deliver a memory write instruction. The memory write instruction includes to-be-written data and a destination address of the to-be-written data. The destination address is a memory address of a destination end device. The first RDMA network interface card is configured to encapsulate the to-be-written data based on the destination address of the to-be-written data and configuration information of the destination end device and send the encapsulated to-be-written data to a second RDMA network interface card of the destination end device.

First claim

What is claimed is:

1. A processor system, applied to a source end device, wherein the processor system comprises a processor core, a first remote direct memory access (RDMA) network interface card, and an interconnection bus, the interconnection bus is connected to the processor core and at least one RDMA network interface card, and the at least one RDMA network interface card comprises the first RDMA network interface card; and wherein:
the processor core is configured to deliver a memory write instruction, wherein the memory write instruction comprises to-be-written data and a destination address of the to-be-written data, the destination address is a memory address of a destination end device, the memory write instruction comprises a first instruction and a second instruction, the first instruction comprises the to-be-written data and a first address, the second instruction comprises the destination address of the to-be-written data and a second address, and the first address and the second address are addresses in a register in the first RDMA network interface card;
the first RDMA network interface card is configured to:
write the to-be-written data to the register in the first RDMA network interface card based on the first address in the first instruction;
write the destination address of the to-be-written data to the register in the first RDMA network interface card based on the second address in the second instruction;
encapsulate, by the first RDMA network interface card, the to-be-written data based on the destination address of the to-be-written data in the register and configuration information of the destination end device; and
send, by the first RDMA network interface card, the encapsulated to-be-written data to a second RDMA network interface card of the destination end device, wherein the second RDMA network interface card writes the to-be-written data to a memory of the destination end device; and

the interconnection bus is configured to:
receive the memory write instruction delivered by the processor core;
determine, from the at least one RDMA network interface card based on a first mapping relationship, the first RDMA network interface card corresponding to the destination address of the to-be-written data; and
send the to-be-written data to the first RDMA network interface card, wherein the first mapping relationship is a mapping relationship between an address window and an address of an RDMA network interface card.

2. The processor system according to claim 1 , wherein:
the first RDMA network interface card is further configured to obtain the configuration information of the destination end device, wherein the configuration information of the destination end device comprises at least one of an address of the destination end device or an address of the second RDMA network interface card.

3. The processor system according to claim 1 , wherein the interconnection bus is configured to:
determine a first address window to which the destination address of the to-be-written data belongs; and
determine, from the at least one RDMA network interface card based on the first mapping relationship, the first RDMA network interface card corresponding to the first address window.

4. The processor system according to claim 1 , wherein the processor system further comprises a memory, and wherein a memory of the source end device and the memory of the destination end device are not addressed uniformly.

5. The processor system according to claim 4 , wherein:
the first RDMA network interface card is further configured to translate the destination address of the to-be-written data based on a second mapping relationship, wherein the second mapping relationship is a mapping relationship between a first memory address and a second memory address, the destination address of the to-be-written data is the first memory address, the first memory address is a mapping address obtained after the memory of the destination end device is mapped to address space of the source end device, the translated destination address is the second memory address, and the second memory address is a local address of the memory of the destination end device; and

the first RDMA network interface card is configured to encapsulate the to-be-written data based on the translated destination address and the configuration information of the destination end device.

6. The processor system according to claim 1 , wherein the processor system further comprises a direct access port, and wherein:
the direct access port is configured to:
receive the memory write instruction from the processor core;
add a timestamp to the memory write instruction;
start a timer in the direct access port; and
send the memory write instruction to the interconnection bus.

7. The processor system according to claim 6 , wherein:
the direct access port is configured to:
stop the timer if receiving a response message of the second RDMA network interface card before the timer expires; or
report timeout response information to the processor core if not receiving a response message of the second RDMA network interface card when the timer expires.

8. The processor system according to claim 7 , wherein the first RDMA network interface card is further configured to:
after receiving the response message of the second RDMA network interface card, maintain a data structure of a data encapsulation protocol on the first RDMA network interface card.

9. A memory access system, comprising a source end device and a destination end device, wherein a processor system of the source end device comprises a processor core and a first remote direct memory access RDMA network interface card, and a processor system of the destination end device comprises a second RDMA network interface card and a memory, wherein:
the processor core of the source end device is configured to deliver a memory read instruction, wherein the memory read instruction comprises an address of to-be-read data and a register address, the address of the to-be-read data is a memory address of the destination end device, and the register address is an address in a register of the processor core;
the first RDMA network interface card is configured to:
encapsulate the register address based on the address of the to-be-read data and configuration information of the destination end device; and
send a read request comprising an encapsulated register address to the second RDMA network interface card of the destination end device;

the second RDMA network interface card is configured to:
receive the read request from the first RDMA network interface card;
decapsulate the encapsulated register address;
read the to-be-read data from a memory of the destination end device based on the address of the to-be-read data;
encapsulate the to-be-read data based on the register address and configuration information of the source end device; and
send the encapsulated to-be-read data to the first RDMA network interface card;
after sending the encapsulated to-be-read data to the first RDMA network interface card, maintain a data structure of a data encapsulation protocol on the second RDMA network interface card; and

the first RDMA network interface card is further configured to:
receive the encapsulated to-be-read data from the second RDMA network interface card;
after receiving the encapsulated to-be-read data sent by the second RDMA network interface card, maintain a data structure of a data encapsulation protocol on the first RDMA network interface card;

decapsulate the encapsulated to-be-read data; and
send the decapsulated to-be-read data to the register of the processor core.

10. The memory

Assignees

• Huawei Tech Co Ltd

Inventors

• Hu Yao
• Wu Pei
• Zhu Xiaoping

Classifications

• G06F15/17331

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• H04L12/4604

  LAN interconnection over a backbone network, e.g. Internet, Frame Relay · CPC title