Electronic device comprising antenna

Patent metadata

Field	Value
Publication number	US-12424732-B2
Application number	US-202218074952-A
Country	US
Kind code	B2
Filing date	Dec 5, 2022
Priority date	Jun 5, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An electronic device is provided. The electronic device includes a printed circuit board (PCB) including a plurality of layers, a communication circuit electrically coupled to the PCB, and at least one processor electrically coupled to the communication circuit. The PCB may include a first layer in which a plurality of patch antennas disposed, a first feeding path which feeds a first point of a first patch antenna so that the first patch antenna disposed to the first layer transmits and/or receives a first polarized signal, a second feeding path which feeds a second point of the first patch antenna so that the first patch antenna disposed to the first layer transmits and/or receives a second polarized signal orthogonal to the first polarized signal, a second layer including a ground, a first ground path, and a second ground.

First claim

What is claimed is:

1. An electronic device comprising:
a printed circuit board (PCB) including a plurality of layers including a first layer and a second layer;
a plurality of patch antennas including a first patch antenna;
a communication circuit electrically coupled to the PCB; and
at least one processor electrically coupled to the communication circuit,

wherein the PCB includes:
the first layer in which the plurality of patch antennas are disposed,
a first feeding path which feeds power directly or indirectly to a first point of the first patch antenna such that the first patch antenna disposed in the first layer transmits and/or receives a first polarized signal,
wherein the first feeding path includes a via penetrating a first number of layers among the plurality of layers and is electrically coupled to the communication circuit,
a second feeding path which feeds power directly or indirectly to a second point of the first patch antenna such that the first patch antenna disposed in the first layer transmits and/or receives a second polarized signal orthogonal to the first polarized signal,
wherein the second feeding path includes a via penetrating the first number of layers among the plurality of layers and is electrically coupled to the communication circuit,

the second layer including a ground,
a first ground path which electrically connects the ground and a third point adjacent to the first point of the first patch antenna, wherein the third point is disposed from the outside of the first patch antenna, and
a second ground path which electrically connects the ground and a fourth point adjacent to the second point of the first patch antenna, wherein the fourth point is disposed from the outside of the first patch antenna.

2. The electronic device of claim 1 , wherein the PCB includes:
a third layer in which a plurality of patch antennas including a second patch antenna are disposed;
a third feeding path which feeds power directly or indirectly to a fifth point of the second patch antenna such that the second patch antenna disposed in the third layer receives a third polarized signal; and
a fourth feeding path which feeds power directly or indirectly to a sixth point of the second patch antenna such that the second patch antenna receives a fourth polarized signal orthogonal to the third polarized signal.

3. The electronic device of claim 2 ,
wherein the third feeding path includes a via penetrating a second number of layers among the plurality of layers and is electrically coupled to the communication circuit, and wherein the fourth feeding path includes a via penetrating the second number of layers among the plurality of layers and is electrically coupled to the communication circuit.

4. The electronic device of claim 2 , wherein the first layer is disposed between the third layer and the second layer.

5. The electronic device of claim 2 ,
wherein, when viewed from above the PCB, the first patch antenna is disposed such that at least two regions of the first patch antenna overlap with at least two regions of the second patch antenna, and
wherein a size of the first patch antenna is greater than a size of the second patch antenna.

6. The electronic device of claim 1 , wherein a width of the ground is 3 mm to 4 mm.

7. The electronic device of claim 1 , wherein a first virtual line connecting the first point and the third point is orthogonal to a second virtual line connecting the second point and the fourth point.

8. The electronic device of claim 1 , wherein the first ground path and the second ground path are disposed not to overlap with a metal frame included in the electronic device, when viewed from a side face of the electronic device.

9. The electronic device of claim 1 , wherein the total number of the plurality of patch antennas is n×m, wherein the plurality of patch antennas are arranged in a rectangular grid, and disposed as an antenna array of an n×m array, and wherein n and m integers are equal to or greater than one.

10. The electronic device of claim 1 , wherein the plurality of patch antennas have at least any one of a circular shape, an oval shape, or a rectangular shape.

11. The electronic device of claim 2 ,
wherein the first patch antenna and the second patch antenna transmit and/or receive a radio frequency (RF) signal of a specified frequency band, and wherein the specified frequency band includes a mm wave band.

12. The electronic device of claim 11 ,
wherein the first patch antenna transmits and/or receives a signal of a frequency band of 24 to 29.5 GHZ, and wherein the second patch antenna transmits and/or receives a signal of a frequency band of 37 to 40 GHz.

13. The electronic device of claim 1 , wherein the first ground path and the second ground path penetrate a third number of layers.

14. The electronic device of claim 1 , wherein the PCB further includes a plurality of dipole antennas.

15. The electronic device of claim 14 , wherein the plurality of dipole antennas are disposed as an antenna array of an n×m array at positions corresponding to the plurality of patch antennas, and wherein n and m integers are equal to or greater than one.

16. An antenna circuit comprising:
a printed circuit board (PCB) including a plurality of layers including a first layer and a second layer;
a plurality of patch antennas including a first patch antenna; and
a communication circuit disposed on a first surface of the PCB,
wherein the PCB includes:
the first layer in which the plurality of patch antennas are disposed;
a first feeding path configured to feed power directly or indirectly to a first point of the first patch antenna such that the first patch antenna disposed in the first layer receives a first polarized signal,
wherein the first feeding path includes a via penetrating a first number of layers among the plurality of layers and is electrically connected to the communication circuit;
a second feeding path configured to feed power directly or indirectly to a second point of the first patch antenna such that the first patch antenna disposed in the first layer receives a second polarized signal orthogonal to the first polarized signal,
wherein the second feeding path includes a via penetrating the first number of layers among the plurality of layers and is electrically connected to the communication circuit;
the second layer corresponding to a ground of the PCB;
a first ground path which electrically connects the second layer and a third point adjacent to the first point of the first patch antenna, wherein the third point is disposed outside of the first patch antenna; and
a second ground path which electrically connects the second layer and a fourth point adjacent to the second point of the first patch antenna, wherein the fourth point is disposed outside of the first patch antenna.

17. The antenna circuit of claim 16 , further comprising:
a third layer in which a plurality of patch antennas including a second patch antenna are disposed; a third feeding path which feeds power directly or indirectly to a fifth point of the second patch antenna such that the second patch antenna disposed to the third layer receives a third polarized signal; and a fourth feeding path which feeds power directly or indirectly to a sixth point of the second patch antenna such that the second patch antenna receives a fourth polarized signal orthogonal to the third polarized signal.

18. The antenna circuit of claim 17 ,
wherein the third feeding path includes a via penetrating a second number of l

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Seongjin
• Kim Hosaeng
• Yun Sumin
• Lee Chaejun
• Jang Woomin
• Jeong Myunghun
• Jong Jehun
• Jo Jaehoon

Classifications

• H01Q21/065

  Patch antenna array · CPC title

• H01Q21/062

  using dipole aerials; (H01Q21/067, H01Q21/068 take precedence) · CPC title

• H01Q9/045

  with particular feeding means (for circular polarisation H01Q9/0428) · CPC title

• H01Q1/48 Primary

  Earthing means; Earth screens; Counterpoises · CPC title

• H01Q9/40

  Element having extended radiating surface · CPC title