Semiconductor structure and method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-12424552-B2
Application number	US-202117448708-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A method of manufacturing a semiconductor structure includes a number of operations. A first oxide layer is provided on a semiconductor integrated circuit. A conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer. An etch stop layer is formed on the top surface of the first oxide layer. A second oxide layer is formed on the etch stop layer. A through via is formed extending through the second oxide layer and the etch stop layer to expose the conductive layer. Acid is provided on the conductive layer to form a protective layer on the conductive layer. The protective layer includes a compound of the acid and material of the conductive layer. A fence of the second oxide layer at an edge on the through via is removed at the through via by a hydrofluoric acid etching.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing a first oxide layer on a semiconductor integrated circuit, wherein a conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer;
forming an etch stop layer on the top surface of the first oxide layer;
forming a second oxide layer on the etch stop layer;
forming a through via extending through the second oxide layer and the etch stop layer to expose the conductive layer and form a fence that is a portion of the second oxide layer and protrudes from an edge of the through via;
providing a fluid of an acid that is spaced apart from the second oxide layer on the conductive layer exposed from the through via in the etch stop layer to form a protective layer on a top surface of the conductive layer, wherein the protective layer comprises a compound of the acid and a material of the conductive layer; and
removing the fence by a wet etching, wherein the protective layer has a greater resistance against the wet etching than the fence.

2. The method of claim 1 , wherein the acid is citric acid.

3. The method of claim 2 , wherein the fluid of the citric acid has a pH value in a range between two and four.

4. The method of claim 1 , wherein the material of the conductive layer is copper.

5. The method of claim 1 , wherein the wet etching is a hydrofluoric acid etching.

6. The method of claim 5 , further comprising:
forming a trench recessed from a top of the second oxide layer, wherein the trench is aligned with the through via, a width of the trench is greater than a width of the through via, and the fence is located at a bottom of the trench and surrounds the through via to form a ring.

7. The method of claim 6 , wherein the width of the trench is increased to a determined critical dimension after the fence is removed by the hydrofluoric acid etching.

8. The method of claim 6 , wherein forming the trench from the top of the second oxide layer further comprises:
forming a photo-resist layer on the top of the second oxide layer, wherein the photo-resist layer has an opening corresponding to the width of the trench;
filling an anti-reflective coating in the through via; and
etching the second oxide layer according to the opening of the photo-resist layer to form the trench.

9. The method of claim 8 , wherein the anti-reflective coating filled in the through via is located on the etch stop layer, and the forming the through via extending through the second oxide layer and the etch stop layer to expose the conductive layer further comprises:
removing the anti-reflective coating filled in the through via; and
extending the through via within the second oxide layer through the etch stop layer to the conductive layer.

10. The method of claim 1 , further comprising:
filling a conductive material in the through via.

Assignees

• Nanya Technology Corp

Inventors

• Wang Chun-Wei
• Lai Jen-I
• Wang Rou-Wei

Classifications

• H10P50/283 Primary

  by chemical means · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title