Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12424496-B2
Application number	US-202218065082-A
Country	US
Kind code	B2
Filing date	Dec 13, 2022
Priority date	Dec 17, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, comprising:
preparing a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other;
forming a roughened layer by grinding the second surface of the semiconductor wafer, the roughened layer having a surface roughness larger than a surface roughness of the second surface of the semiconductor wafer before grinding;
pressing a blade against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer;
removing the roughened layer after forming the vertical crack;
forming a rear surface electrode on a rear surface of the semiconductor wafer on which the vertical crack is formed; and
after forming the rear surface electrode, pressing the first surface of the semiconductor wafer, and cleaving the semiconductor wafer into a plurality of pieces with the vertical crack as a starting point.

2. The manufacturing method according to claim 1 , wherein
the forming the roughened layer is performed in a state where the first surface of the semiconductor wafer is attached with a protective tape or a support substrate to protect the first surface.

3. The manufacturing method according to claim 1 , wherein
the removing the roughened layer includes removing the roughened layer by polishing.

4. The manufacturing method according to claim 1 , wherein
the preparing the semiconductor wafer includes preparing the semiconductor wafer that is made of silicon carbide, and
the removing the roughened layer includes silicidizing the rear surface electrode and the roughened layer after forming the rear surface electrode covering the roughened layer.

5. The manufacturing method according to claim 4 , wherein
the forming the rear surface electrode includes forming the rear surface electrode in which a portion being in contact with the roughened layer is composed mainly of at least one metal material selected from a group consisting of Ni, Ti, Mo, Ta, Pt, and Co, and
the removing the roughened layer includes silicidizing the rear surface electrode and the roughened layer by heat treatment.

6. The manufacturing method according to claim 4 , wherein
the forming the rear surface electrode includes forming the rear surface electrode having a thickness larger than a thickness of the roughened layer.

Assignees

• Denso Corp
• Toyota Motor Co Ltd
• MIRISE Technologies Corporation

Inventors

• Nagumo Yuji
• Uecha Masashi
• Tsuma Hiroki
• Kumazawa Teruaki

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10D64/0115

  to silicon carbide · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title