Digital verify failbit count (VFC) circuit

Patent metadata

Field	Value
Publication number	US-12424299-B2
Application number	US-202318339280-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Dec 30, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A verify failbit count (VFC) circuit includes a counter including a plurality of counter stages coupled one after another and including one or more cache stages in a cache group and a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages. Each of the reception stages is configured to receive one of a plurality of verification bits generated by a verification operation of a memory device. The counter further includes one or more switches each coupled between two neighboring ones of the plurality of reception groups.

First claim

What is claimed is:

1. A verify failbit count (VFC) circuit comprising:
a counter configured to count fail bits among a plurality of verification bits generated by a verification operation of a memory device to obtain a count result in binary format;
wherein the counter includes:
a plurality of counter stages coupled one after another, the plurality of counter stages including:
one or more cache stages in a cache group; and
a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages, and each of the reception stages being configured to receive a different one of the plurality of verification bits; and

one or more switches each coupled between two neighboring ones of the plurality of reception groups.

2. The VFC circuit of claim 1 , wherein each of the plurality of counter stages includes a counter latch.

3. The VFC circuit of claim 2 , wherein each of the plurality of counter stages further includes:
a first transistor coupled between a first terminal of the counter latch and a ground; and
a second transistor coupled between a second terminal of the counter latch and the ground.

4. The VFC circuit of claim 3 , wherein each of the plurality of counter stages further includes:
a ground transistor coupled between:
the ground, and
each of the first transistor and the second transistor.

5. The VFC circuit of claim 2 , wherein each of the one or more cache stages further includes a transistor string coupled between the counter latch of the cache stage and a power supply line, the transistor string including a plurality of transistors coupled in series.

6. The VFC circuit of claim 5 , wherein a gate of one of the plurality of transistors is coupled to a terminal of the counter latch of the cache stage.

7. The VFC circuit of claim 2 , wherein:
each of the plurality of reception stages further includes:
a first transistor string coupled between a first terminal of the counter latch of the reception stage and a power supply line; and
a second transistor string coupled between a second terminal of the counter latch of the reception stage and the power supply line; and

each of the first transistor string and the second transistor string includes a plurality of transistors coupled in series.

8. The VFC circuit of claim 1 , wherein the plurality of reception groups include:
a first reception group directly coupled to the cache group without via any of the one or more switches; and
one or more second reception groups each coupled to the cache group via at least one of the one or more switches.

9. The VFC circuit of claim 8 , wherein:
each of the plurality of counter stages includes a counter latch;
the counter latch in each of the plurality of reception stages is configured to latch one of the plurality of verification bits;
the counter latch in each of the one or more reception stages in the first reception group is further configured to store a part of the count result; and
the counter latch in each of the one or more cache stages is configured to store another part of the count result.

10. The VFC circuit of claim 8 , wherein:
the one or more switches are coupled in a power supply line of the VFC circuit, the power supply line being coupled to a power supply; and
the one or more switches are configured to control power supply to the one or more second reception groups.

11. The VFC circuit of claim 1 ,
wherein the counter is one of a plurality of counters;
the VFC circuit further comprising:
an adder configured to sum up the count results from two or more of the plurality of counters.

12. The VFC circuit of claim 1 ,
wherein the VFC circuit includes a plurality of VFC sub-circuits, and the counter belongs to one of the plurality of VFC sub-circuits;
the VFC circuit further comprising:
an accumulator coupled to the plurality of VFC sub-circuits and configured to accumulate final binary sums output from the plurality of VFC sub-circuits.

13. A failbit counting method comprising:
controlling a counter of a verify failbit count (VFC) circuit of a memory device to receive a plurality of verification bits generated by a verification operation of the memory device; and
controlling the counter to count fail bits among the plurality of verification bits to obtain a count result in binary format;
wherein the counter includes:
a plurality of counter stages coupled one after another, the plurality of counter stages including:
one or more cache stages in a cache group; and
a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages, and each of the reception stages being configured to receive a different one of the plurality of verification bits; and

one or more switches each coupled between two neighboring ones of the plurality of reception groups.

14. A memory device comprising:
a memory cell array including a plurality of memory cells; and
the verify failbit count (VFC) circuit of claim 1 and coupled to the memory cell array.

15. A verify failbit count (VFC) circuit comprising:
a counter configured to count fail bits among a plurality of verification bits generated by a verification operation of a memory device to obtain a count result in binary format;
wherein the counter includes:
a plurality of counter stages coupled one after another, the plurality of counter stages including:
two cache stages in a cache group; and
N reception stages divided into a plurality of reception groups each including M reception stages of the N reception stages, each of the reception stages being configured to receive one of the plurality of verification bits, N being an integer that is a power of 2, and M being an integer that is a power of 2 and smaller than or equal to N/2; and

one or more switches each coupled between two neighboring ones of the plurality of reception groups.

16. The method of claim 13 , wherein:
each of the plurality of counter stages has a first storage state and a second storage state, and the first storage state and the second storage state of a reception stage are used to represent that the reception stage stores a fail bit and a pass bit, respectively, after the verification bits are received by the counter; and
controlling the counter to count fail bits to obtain the count result in binary format includes:
determining storage states of the plurality of counter stages; and
controlling the storage states of the plurality of counter stages according to the determined storage states and a set of rules until the storage state of each of one or more reception stages except one or more designated reception stages is in the second storage state, the storage states of the one or more cache stages and the one or more designated reception stages representing the count result in binary format.

17. The method of claim 16 , wherein:
the one or more cache stages include a first cache stage and a second cache stage coupled to each other;
the plurality of reception stages include N reception stages coupled to each other, a first reception stage of the N reception stages being coupled to the second cache stage, and N being an integer that is a power of 2;
each of the reception groups includes M reception stages, M being an integer that is a power of 2 and smaller than or equal to N/2; and
controlling the counter to count fail bits to obtain the count result in binary format includes:
determining whether the N reception st

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Teng
• Guo Xiaojiang
• Kuriyama Masao

Classifications

• G11C29/56016

  Apparatus features · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title