Method of operating memory device and memory device performing the same

Patent metadata

Field	Value
Publication number	US-12424289-B2
Application number	US-202318465541-A
Country	US
Kind code	B2
Filing date	Sep 12, 2023
Priority date	Dec 29, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

In a method of operating a memory device, a first operation is performed on a memory block by applying first driving voltages to a plurality of wordlines. After the first operation is completed, a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged is performed. After the first recovery operation is completed, a second operation is performed on the memory block by applying second driving voltages to the plurality of wordlines. In the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline. In the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.

First claim

What is claimed is:

1. A method of operating a memory device including a memory block connected to a plurality of wordlines, the method comprising:
performing a first operation on the memory block by applying first driving voltages to the plurality of wordlines;
after the first operation is completed, performing a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged; and
after the first recovery operation is completed, performing a second operation on the memory block by applying second driving voltages to the plurality of wordlines,
wherein, in the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline, and
wherein, in the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.

2. The method of claim 1 , wherein an operation of storing the first charges in the charge recycling memory block and an operation of applying the second driving voltages using the first charges are performed based on a charge sharing operation.

3. The method of claim 2 , wherein the operation of storing the first charges in the charge recycling memory block and the operation of applying the second driving voltages using the first charges are performed using capacitances of charge recycling memory cells included in the charge recycling memory block and a capacitance of the at least one charge recycling wordline.

4. The method of claim 3 ,
wherein the charge recycling memory block and the charge recycling memory cells are a dummy memory block and dummy memory cells in which data is not stored, and
wherein the at least one charge recycling wordline is a dummy wordline.

5. The method of claim 1 ,
wherein the first operation is a first read operation performed on a first page that is included in the memory block and connected to a first wordline among the plurality of wordlines, and
wherein the second operation is a second read operation performed on a second page that is included in the memory block and connected to a second wordline different from the first wordline among the plurality of wordlines.

6. The method of claim 5 , wherein the performing the first operation includes:
applying a read voltage to the first wordline; and
applying a read inhibit voltage to wordlines other than the first wordline among the plurality of wordlines.

7. The method of claim 5 , wherein the performing the first recovery operation includes:
electrically connecting the plurality of wordlines with the at least one charge recycling wordline; and
performing a first discharging operation in which voltage levels of the plurality of wordlines decrease, and
wherein the first charges move to the charge recycling memory block through the at least one charge recycling wordline by a charge sharing operation.

8. The method of claim 7 , wherein the performing the first recovery operation further includes:
electrically disconnecting the plurality of wordlines from the at least one charge recycling wordline; and
performing a second discharging operation in which the voltage levels of the plurality of wordlines additionally decrease.

9. The method of claim 5 , wherein the performing the second operation includes:
electrically connecting the plurality of wordlines with the at least one charge recycling wordline; and
performing a first charging operation in which voltage levels of the plurality of wordlines increase, and
wherein the first charges move to the plurality of wordlines through the at least one charge recycling wordline by a charge sharing operation.

10. The method of claim 9 , wherein the performing the second operation further includes:
electrically disconnecting the plurality of wordlines from the at least one charge recycling wordline;
electrically connecting a charge pump with the at least one charge recycling wordline; and
performing a second charging operation in which the voltage levels of the plurality of wordlines additionally increase using the charge pump.

11. The method of claim 1 ,
wherein the first operation is a first program operation performed on a first page that is included in the memory block and connected to a first wordline among the plurality of wordlines, and
wherein the second operation is a first program verification operation performed on the first page.

12. The method of claim 11 , wherein the performing the first operation includes:
applying a program voltage to the first wordline; and
applying a program inhibit voltage to wordlines other than the first wordline among the plurality of wordlines.

13. The method of claim 11 , wherein the performing the first recovery operation includes:
electrically connecting the wordlines other than the first wordline among the plurality of wordlines with the at least one charge recycling wordline; and
performing a first discharging operation in which voltage levels of all of the plurality of wordlines decrease, and
wherein the first charges move to the charge recycling memory block through the at least one charge recycling wordline by a charge sharing operation.

14. The method of claim 11 , wherein the performing the first recovery operation includes:
electrically connecting all of the plurality of wordlines with the at least one charge recycling wordline; and
performing a first discharging operation in which voltage levels of all of the plurality of wordlines decrease, and
wherein the first charges move to the charge recycling memory block through the at least one charge recycling wordline by a charge sharing operation.

15. The method of claim 1 ,
wherein the first operation is a first program operation performed on a first page that is included in the memory block and connected to a first wordline among the plurality of wordlines, and
wherein the second operation is a second program operation performed on the first page.

16. The method of claim 1 , wherein the memory block is a vertical memory block including a plurality of memory cells that are arranged in a vertical direction on a substrate.

17. A memory device comprising:
a memory cell array including a memory block connected to a plurality of wordlines, and a charge recycling memory block connected to at least one charge recycling wordline;
a voltage generator configured to generate a plurality of driving voltages applied to the plurality of wordlines; and
a control circuit configured to control an operation of the memory cell array and an operation of the voltage generator,
wherein the control circuit is configured to:
perform a first operation on the memory block by applying first driving voltages to the plurality of wordlines;
after the first operation is completed, perform a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged; and
after the first recovery operation is completed, perform a second operation on the memory block by applying second driving voltages to the plurality of wordlines,

wherein, in the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in the charge recycling memory block, and
wherein, in the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.

18. The memory devic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chihyun
• Park Junehong
• Yoon Jayang
• Yoon Chiweon
• Choi Hyeongdo

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title