Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

Patent metadata

Field	Value
Publication number	US-12424288-B2
Application number	US-202418738908-A
Country	US
Kind code	B2
Filing date	Jun 10, 2024
Priority date	Mar 7, 2019
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device; and
performing a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions, wherein performing the program targeting operation comprises:
selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution; and
adjusting, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

2. The system of claim 1 , wherein the last programming distribution corresponds to one of the programming distributions of the memory cell having a highest PV target.

3. The system of claim 1 , wherein the predefined set of rules further corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution.

4. The system of claim 1 , wherein the predefined set of rules further corresponds to a locking of a PV target of a programming distribution adjacent to an initial programming distribution.

5. The system of claim 1 , wherein the program targeting operation implements the predefined set of rules to balance logical page types such that a bit error rate (BER) is approximately a same BER for different logical page types, and to equalize relative widths of valleys of a particular logical page type such that read window budgets (RWB) for the valleys of the particular logical page type are approximately a same RWB.

6. The system of claim 1 , wherein selecting the rule from the predefined set of rules based on the plurality of computing error metrics, comprises:
identifying a first logical page type and a second logical page type; and
determining whether a bit error rate (BER) for the first logical page type is less than or greater than a BER for the second logical page type; and
responsive to determining that the BER for the first logical page type is less than the BER for the second logical page type, identifying a first subset of the predefined set of rules, wherein the selected rule is from the first subset of rules.

7. The system of claim 6 , wherein selecting the rule from the predefined set of rules based on the plurality of computing error metrics, comprises:
responsive to determining that the BER for the first logical page type is greater than the BER for the second logical page type, identifying a second subset of the predefined set of rules, wherein the selected rule is from the second subset of rules.

8. The system of claim 6 , wherein determining whether the BER for the first logical page type is less than or greater than the BER for the second logical page type, comprises:
comparing a first average center bit error count associated with the first logical page type to a second average center bit error count associated with the second logical page type, wherein the BER for the first logical page type is less than the BER for the second logical page type when the first average center bit error count is less than the second average center bit error count, and wherein the BER for the first logical page type is greater than the BER for the second logical page type when the first average center bit error count is greater than the second average center bit error count.

9. The system of claim 6 , the operations further comprising:
identifying a rule from the first subset of rules based on a valley that has a largest relative width for the first logical page type and a valley that has a least relative width for the second logical page type.

10. The system of claim 9 , wherein the plurality of computing error metrics are used to determine the valley that has the largest relative width for the first logical page type and the valley that has the least relative width for the second logical page type.

11. The system of claim 1 , wherein selecting the rule from the predefined set of rules based on the plurality of computing error metrics, comprises:
selecting the rule from the predefined set of rules that identifies at least two program verify (PV) targets describing an adjusting such that a relative width of a valley that has a lowest difference error count (Diff-EC) for a first logical page type is decreased and a relative width of a valley that has a highest Diff-EC for a second logical page type is increased.

12. The system of claim 1 , wherein the program targeting operation is performed responsive to a satisfaction of one or more conditions.

13. A method comprising:
determining, by a processing device, a plurality of difference error counts (Diff-EC) that are indicative of relative widths of valleys, wherein each of the valleys is located between a respective pair of program distributions of memory cells of a memory device; and
performing a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions, wherein performing the program targeting operation comprises:
selecting a rule from a predefined set of rules based on the plurality of difference error counts, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution; and
adjusting, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

14. The method of claim 13 , wherein the last programming distribution corresponds to one of the programming distributions of the memory cell having a highest PV target.

15. The method of claim 13 , wherein the predefined set of rules further corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution.

16. The method of claim 13 , wherein the predefined set of rules further corresponds to a locking of a PV target of a programming distribution adjacent to an initial programming distribution.

17. The method of claim 13 , wherein the program targeting operation implements the predefined set of rules to balance logical page types such that a bit error rate (BER) is approximately a same BER for different logical page types, and to equalize relative widths of valleys of a particular logical page type such that read window budgets (RWB) for the valleys of the particular logical page type are approximately a same RWB.

18. A non-transitory computer-readable medium comprising instructions that, responsive to execution by a processing device, cause the processing device to perform operations comprising:
determining a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within a memory device; and
performing a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions, where

Assignees

• Micron Technology Inc

Inventors

• Liikanen Bruce A
• Koudele Larry J
• Sheperek Michael

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2211/5624

  Concurrent multilevel programming and programming verification · CPC title

• G11C2211/5625

  Self-converging multilevel programming · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2211/5623

  Concurrent multilevel programming and reading · CPC title