Memory and operating method therefor

Patent metadata

Field	Value
Publication number	US-12424268-B2
Application number	US-202318157059-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Sep 15, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

First claim

What is claimed is:

1. A memory, comprising:
a memory cell array;
a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array;
a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and
a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information outputted by the memory cell array based on the read operation;
wherein the read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array;
wherein the memory cell array comprises a first target memory cell and a second target memory cell located in a same column, the first target memory cell being closer to the second column decoder than the second target memory cell;
the second column decoder is configured to transmit a second column selection signal, to select the first target memory cell and the second target memory cell to perform the read operation;
the first target memory cell is configured to output, during a first read period, first read data to the read amplifier according to the second column selection signal;
the read amplifier is further configured to receive the first read data after a first read time since the second column decoder transmits the second column selection signal;
the second target memory cell is configured to output, during a second read period, second read data to the read amplifier according to the second column selection signal;
the read amplifier is further configured to receive the second read data after a second read time since the second column decoder transmits the second column selection signal;
wherein the first read time and the second read time are the same.

2. The memory according to claim 1 , further comprising:
a command decoder, coupled to the first column decoder and configured to control the first column decoder to perform the write operation according to a received write operation command;
wherein the command decoder is coupled to the second column decoder and further configured to control the second column decoder to perform the read operation according to a received read operation command.

3. The memory according to claim 1 , further comprising;
a first column selection line, coupled to the first column decoder and the memory cell array and configured to transmit a first column selection signal to the memory cell array in the first direction, wherein the first column selection signal is used to select a memory cell column in the memory cell array for performing the write operation; and
a second column selection line, coupled to the second column decoder and the memory cell array and configured to transmit a second column selection signal to the memory cell array in a second direction opposite to the first direction, wherein the second column selection signal is used to select a memory cell column in the memory cell array for performing the read operation.

4. The memory according to claim 1 , further comprising: a write driver, wherein
the write driver and the first column decoder are located on a same side of the memory cell array, and the write driver is configured to transmit a data signal to be written to the memory cell array according to a received write operation command.

5. The memory according to claim 1 , further comprising:
a row decoder, coupled to the memory cell array, the row decoder and the memory cell array being arranged in a third direction, the third direction being perpendicular to the first direction;
wherein the row decoder is configured to transmit a row selection signal to the memory cell array, to select a memory cell row performing the write operation or the read operation in the memory cell array.

6. The memory according to claim 1 , wherein the memory comprises a dynamic random access memory.

7. An operating method for a memory, comprising:
performing, by a first column decoder in the memory in a case where a write operation is performed, the write operation on a memory cell array in the memory;
performing, by a second column decoder in the memory in a case where a read operation is performed, the read operation on the memory cell array; and
receiving, by a read amplifier in the memory, read data information output by the memory cell array based on the read operation, wherein the read amplifier, the first column decoder, the memory cell array and the second column decoder is arranged in a first direction, the first column decoder and the second column decoder is located on two opposite sides of the memory cell array, and the read amplifier and the second column decoder are located on two opposite sides of the memory cell array;
wherein performing, by the second column decoder in the memory, the read operation on the memory cell array comprises:
transmitting, by the second column decoder, a second column selection signal, to select a first target memory cell and a second target memory cell in the memory to perform the read operation, wherein the first target memory cell is closer to the second column decoder than the second target memory cell;
outputting, by the first target memory cell during a first read period, first read data to the read amplifier according to the second column selection signal;
receiving, by the read amplifier, the first read data after a first read time since the second column decoder transmits the second column selection signal;
outputting, by the second target memory cell during a second read period, second read data to the read amplifier according to the second column selection signal; and
receiving, by the read amplifier, the second read data after a second read time since the second column decoder transmits the second column selection signal;
wherein the first read time and the second read time are the same.

8. The operating method for a memory according to claim 7 , further comprising:
in the case where the write operation is performed, controlling, by a command decoder in the memory, the first column decoder to perform the write operation according to a received write operation command; and
in the case where the read operation is performed, controlling, by the command decoder, the second column decoder to perform the read operation according to a received read operation command.

9. The operating method for a memory according to claim 7 , wherein performing, by the first column decoder in the memory, the write operation on the memory cell array in the memory comprises:
transmitting, by the first column decoder, a first column selection signal through a first column selection line in the memory in the first direction, to select a memory cell column in the memory cell array for performing the write operation;
wherein the first column selection line is coupled to the first column decoder and the memory cell array.

10. The operating method for a memory according to claim 7 , wherein performing, by the second column decoder in the memory, the read operation on the memory cell array comprises:
transmitting, by the second column decoder, a second column selection signal through a second column selection line in the memory in a second direction opposite to the first direction, to select a memory cell column in the memory cell array for performing the read operation;
wherein the second column selection line is coupled to the second column decoder and

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title