Display device

Patent metadata

Field	Value
Publication number	US-12424186-B2
Application number	US-202318503201-A
Country	US
Kind code	B2
Filing date	Nov 7, 2023
Priority date	Jan 27, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A display device includes: a multiplexer in a first region of a non-display region, and including K MUX transistors which are commonly connected to a data channel line and are connected to K data lines; a pseudo multiplexer disposed in a third region of the non-display region, and including K pseudo MUX transistors corresponding to the K MUX transistors; and K MUX control lines and K pseudo MUX control lines in a second region between the first and third regions, the K MUX control lines connected to the K MUX transistors, the K pseudo MUX control lines connected to the K pseudo MUX transistors, wherein the second region includes a first partial region adjacent to the first region and having the K MUX control lines thereon, and a second partial area adjacent to the third region and having the K pseudo MUX control lines thereon.

First claim

What is claimed is:

1. A display device, comprising:
a display panel including an array substrate in which a display region on which pixels and data lines connected to the pixels are arranged, and a non-display region adjacent to the display region are defined;
a multiplexer which is disposed in a first region of the non-display region, and includes K (K is an integer of 2 or more) MUX transistors, wherein source electrodes of the K MUX transistors are commonly connected to one data channel line, and drain electrodes of the K MUX transistors are respectively connected to K data lines;
a pseudo multiplexer which is disposed in a third region of the non-display region, and includes K pseudo MUX transistors that are disposed to correspond to the K MUX transistors, respectively; and
K MUX control lines and K pseudo MUX control lines arranged in a second region of the non-display region between the first and third regions of the non-display region, wherein the K MUX control lines are respectively connected to gate electrodes of the K MUX transistors, and the K pseudo MUX control lines are respectively connected to gate electrodes of the K pseudo MUX transistors,
wherein the second region of the non-display region includes a first partial region which is adjacent to the first region of the non-display region and in which the K MUX control lines are arranged, and a second partial area which is adjacent to the third region of the non-display region and in which the K pseudo MUX control lines are arranged.

2. The display device of claim 1 , wherein the gate electrode of the MUX transistor contacts the corresponding MUX control line, and extends in a direction toward the first region of the non-display region.

3. The display device of claim 1 , wherein the gate electrode of the pseudo MUX transistor contacts the corresponding pseudo MUX control line, and extends toward the third region of the non-display region.

4. The display device of claim 1 , wherein the MUX transistor and the pseudo MUX transistor corresponding to each other are arranged to face each other with the second region of the non-display region therebetween.

5. The display device of claim 1 , wherein a MUX control signal and a pseudo MUX control signal applied to the MUX control line and the pseudo MUX control line, respectively, which are connected to the MUX transistor and the pseudo MUX transistor corresponding to each other, respectively, have phases opposite to each other.

6. The display device of claim 1 , wherein a source electrode and a drain electrode of the pseudo MUX transistor are short circuited.

7. The display device of claim 6 , wherein the source electrode and the drain electrode of the pseudo MUX transistor are connected to a voltage line to which a DC voltage of 0V or less is applied.

8. The display device of claim 6 , wherein the source electrode and the drain electrode of the pseudo MUX transistor are connected to a voltage line to which a gate low voltage of gate lines in the display panel is applied.

9. The display device of claim 1 , wherein the display panel is a liquid crystal display panel, or a light emitting display panel including a light emitting diode.

10. The display device of claim 1 , wherein the first region is closer to the display region than the third region.

11. A display device, comprising:
a multiplexer which is in a display panel and is connected between data lines and one data channel line;
a pseudo multiplexer which is in the display panel and is spaced apart from the multiplexer in a first direction in which the data lines extend; and
MUX control lines and pseudo MUX control lines between the multiplexer and the pseudo multiplexer, the MUX control lines extending along a second direction crossing the first direction and connected to the multiplexer, the pseudo MUX control lines extending along the second direction and connected to the pseudo multiplexer,
wherein the MUX control lines are disposed between the multiplexer and the pseudo MUX control lines.

12. The display device of claim 11 , wherein the multiplexer includes K MUX transistors which are respectively connected to K (K is an integer of 2 or more) data lines and are respectively connected to K MUX control lines, and
wherein a gate electrode of the MUX transistor contacts the corresponding MUX control line and extends in the first direction.

13. The display device of claim 12 , wherein the gate electrode of the MUX transistor does not overlap the pseudo MUX control lines.

14. The display device of claim 11 , wherein the pseudo multiplexer includes K pseudo MUX transistors respectively connected to K pseudo MUX control lines, and
wherein a gate electrode of the pseudo MUX transistor contacts the corresponding pseudo MUX control line and extends in the first direction.

15. The display device of claim 14 , wherein the gate electrode of the pseudo MUX transistor does not overlap the MUX control lines.

16. The display device of claim 11 , wherein a MUX control signal and a pseudo MUX control signal which are applied to the MUX control line and the pseudo MUX control line, respectively, corresponding to each other have phases opposite to each other.

17. The display device of claim 11 , wherein input terminal and output terminal of the pseudo multiplexer are short circuited.

18. The display device of claim 17 , wherein the input terminal and output terminal of the pseudo multiplexer are connected to a voltage line to which a DC voltage of 0V or less is applied.

19. The display device of claim 11 , wherein the display panel is a liquid crystal display panel, or a light emitting display panel including a light emitting diode.

20. The display device of claim 11 , wherein the pseudo multiplexer is located closer to the outside of the display panel than the multiplexer.

Assignees

• Lg Display Co Ltd

Inventors

• Lee Da-Hee

Classifications

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title