Display panel and display device

Patent metadata

Field	Value
Publication number	US-12424154-B2
Application number	US-202418735300-A
Country	US
Kind code	B2
Filing date	Jun 6, 2024
Priority date	May 6, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

First claim

What is claimed is:

1. A display panel, comprising a display area;
wherein the display panel further comprises:
a light-emitting element, wherein the light-emitting element is located in the display area;
a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;
a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and
pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect;
wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded, and at least one stage of shift register circuit is located between adjacent pixel circuit rows;
the shift register circuits comprise odd-numbered stages of shift register circuits and even-numbered stages of shift register circuits;
the odd-numbered stages of shift register circuits are arranged along the second direction, and the even-numbered stages of shift register circuits are arranged along the second direction; and
the odd-numbered stages of shift register circuits and the even-numbered stages of shift register circuits are arranged along the first direction;
wherein the shift register circuit at least comprises a latch module and a buffer module;
along the first direction, the latch module of an odd-numbered stage of shift register circuit is located on a side of the buffer module facing an even-numbered stage of shift register circuit, and the latch module of the even-numbered stage of shift register circuit is located on a side of the buffer module facing the odd-numbered stage of shift register circuit.

2. The display panel of claim 1 , wherein at least one of the following is satisfied:
the odd-numbered stages of shift register circuits are electrically connected to a same clock signal line; or
the even-numbered stages of shift register circuits are electrically connected to a same clock signal line.

3. The display panel of claim 1 , wherein
the driver circuit comprises a scan driver circuit, the scan driver circuit is configured to provide a scan signal to the pixel circuit, the scan driver circuit comprises a plurality of stages of scan shift register circuits cascaded, the scan shift register circuit comprises a first latch module and a first buffer module;
along the first direction, the first latch module of an odd-numbered stage of scan shift register circuit is located on a side of the first buffer module facing an even-numbered stage of scan shift register circuit, and the first latch module of the even-numbered stage of scan shift register circuit is located on a side of the first buffer module facing the odd-numbered stage of scan shift register circuit.

4. The display panel of claim 1 , wherein
the driver circuit comprises a light-emitting control driver circuit, the light-emitting control driver circuit is configured to provide a light-emitting control signal to the pixel circuit, the light-emitting control driver circuit comprises a plurality of stages of light-emitting control shift register circuits cascaded, and the light-emitting control shift register circuit comprises a second latch module and a second buffer module;
along the first direction, the second latch module of an odd-numbered stage of light-emitting control shift register circuit is located on a side of the second buffer module facing an even-numbered stage of light-emitting control shift register circuit, and the second latch module of the even-numbered stage of light-emitting control shift register circuit is located on a side of the second buffer module facing the odd-numbered stage of light-emitting control shift register circuit.

5. The display panel of claim 1 , wherein
at least one odd-numbered stage of shift register circuit and at least one even-numbered stage of shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows; or
at least one odd-numbered stage of shift register circuit and at least one even-numbered stage of shift register circuit are located in different gaps between adjacent pixel circuit rows or adjacent light-emitting element rows.

6. The display panel of claim 1 , wherein
in an area of the display area, the odd-numbered stage of shift register circuit and the even-numbered stage of shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows; and
in another area of the display area, the odd-numbered stage of shift register circuit and the even-numbered stage of shift register circuit are located in different gaps between adjacent pixel circuit rows or adjacent light-emitting element rows.

7. The display panel of claim 1 , wherein
along the second direction, at least one odd-numbered stage of shift register circuit and at least one even-numbered stage of shift register circuit do not overlap.

8. The display panel of claim 1 , wherein
the driver circuit comprises a scan driver circuit and a light-emitting control driver circuit, the scan driver circuit is configured to provide a scan signal for the pixel circuit, and the light-emitting control driver circuit is configured to provide a light-emitting control signal for the pixel circuit;
the scan driver circuit comprises a plurality of stages of scan shift register circuits cascaded;
the light-emitting control driver circuit comprises a plurality of stages of light-emitting control shift register circuits cascaded;
wherein the scan driver circuit and the light-emitting control driver circuit are arranged along the first direction.

9. The display panel of claim 8 , wherein at least one of the following is satisfied:
at least one odd-numbered stage of scan shift register circuit and at least one odd-numbered stage of light-emitting control shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows; or
at least one even-numbered stage of scan shift register circuit and at least one even-numbered stage of light-emitting control shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows.

10. The display panel of claim 8 , wherein
at least one odd-numbered stage of scan shift register circuit, at least one even-numbered stage of scan shift register circuit, at least one odd-numbered stage of light-emitting control shift register circuit and at least one even-numbered stage of light-emitting control shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows; or
at least one odd-numbered stage of scan shift register circuit, at least one even-numbered stage of scan shift register circuit and at least one even-numbered stage of light-emitting control shift register circuit are located between same adjacent pixel circuit rows or same adjacent light-emitting element rows.

11. The display panel of claim 8 , wherein
in an area of the display area, at least one of the following is satisfied: the odd-numbered stage of scan shift register circuit and the even-numbered stage of scan shift register circuit are located in different gaps between adjacent pixel circuit rows or adjacent light-emitting element rows, or, the odd-numbered stage of light-emitting control shift register circuit and the even-numbered stage of light-emitting control shift register ci

Assignees

• Hubei Yangtze Ind Innovation Center Of Advanced Display Co Ltd

Inventors

• Dai Wenjun
• Xing Liang
• Wu Tianyi

Classifications

• G02F1/136204

  Arrangements to prevent high voltage or static electricity failures · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title