Shifting register with fewer transistors, driving method, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-12424143-B2
Application number	US-202418650484-A
Country	US
Kind code	B2
Filing date	Apr 30, 2024
Priority date	Jan 3, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

The present disclosure relates to the field of display, and discloses a shifting register, a driving method, a gate driving circuit and a display device. The shifting register includes: an input sub-circuit, coupled to a signal input terminal, a first clock signal terminal and a first node; a control sub-circuit, coupled to the first clock signal terminal, a second clock signal terminal, the signal input terminal, a first power terminal, a second power terminal and a second node, where the first power terminal or the second power terminal determines a potential of the second node under the control of the first clock signal terminal, the second clock signal terminal and the signal input terminal; and an output sub-circuit, coupled to the first power terminal, the second power terminal, the first node, the second node and a signal output terminal.

First claim

What is claimed is:

1. A shifting register, comprising:
an input sub-circuit, coupled to a signal input terminal, a first clock signal terminal and a first node; wherein the input sub-circuit is configured to charge and reset the first node under control of the first clock signal terminal;
a control sub-circuit, coupled to the first clock signal terminal, a second clock signal terminal, the signal input terminal, a first power terminal, a second power terminal and a second node; wherein the control sub-circuit is configured to determine a potential of the second node by the first power terminal or the second power terminal under control of the first clock signal terminal, the second clock signal terminal and the signal input terminal; and
an output sub-circuit, coupled to the first power terminal, the second power terminal, the first node, the second node and a signal output terminal; wherein the output sub-circuit is configured to determine a potential of the signal output terminal by the first power terminal or the second power terminal under control of the first node and the second node;
wherein the control sub-circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate of the first transistor is coupled to the second clock signal terminal, a first electrode of the first transistor is directly coupled to the second power terminal, and a second electrode of the first transistor is coupled to a first electrode of the second transistor;
a second electrode of the second transistor is coupled to a gate of the third transistor, and a gate of the second transistor is directly coupled to the signal input terminal;
a first electrode of the third transistor is coupled to the second clock signal terminal, and a second electrode of the third transistor is coupled to a first electrode of the fourth transistor; and
a gate of the fourth transistor is coupled to the second clock signal terminal.

2. The shifting register according to claim 1 , wherein the input sub-circuit comprises a fifth transistor; and
a gate of the fifth transistor is coupled to the first clock signal terminal, a first electrode of the fifth transistor is coupled to the signal input terminal, and a second electrode of the fifth transistor is coupled to the first node.

3. The shifting register according to claim 1 , wherein the control sub-circuit further comprises a sixth transistor; and
a gate of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the first power terminal, and a second electrode of the sixth transistor is coupled to the gate of the third transistor.

4. The shifting register according to claim 1 , wherein the control sub-circuit further comprises a first capacitor; and
a first terminal of the first capacitor is coupled to the gate of the third transistor, and a second terminal of the first capacitor is coupled to the second electrode of the third transistor.

5. The shifting register according to claim 1 , wherein the output sub-circuit comprises a seventh transistor, an eighth transistor and a second capacitor;
a gate of the seventh transistor is coupled to the first power terminal, a first electrode of the seventh transistor is coupled to a second electrode of a fifth transistor, and a second electrode of the seventh transistor is coupled to a gate of the eighth transistor;
a first electrode of the eighth transistor is coupled to the first power terminal, and a second electrode of the eighth transistor is coupled to the signal output terminal; and
a first terminal of the second capacitor is coupled to the gate of the eighth transistor, and a second terminal of the second capacitor is coupled to the signal output terminal.

6. The shifting register according to claim 1 , wherein the output sub-circuit further comprises a ninth transistor, a tenth transistor and a third capacitor;
a gate of the ninth transistor is coupled to a first electrode of a seventh transistor, a first electrode of the ninth transistor is coupled to the second power terminal, and a second electrode of the ninth transistor is coupled to a gate of the tenth transistor;
a first electrode of the tenth transistor is coupled to the signal output terminal, and a second electrode of the tenth transistor is coupled to the second power terminal; and
a first terminal of the third capacitor is coupled to the gate of the tenth transistor, and a second terminal of the third capacitor is coupled to the second power terminal.

7. A driving method of the shifting register according to claim 1 , comprising:
in a signal holding output period, controlling, by the input sub-circuit, the first node to be in a maintained state according to signals of the input signal terminal and the first clock signal terminal; and controlling, by the control sub-circuit, the second node to be in a maintained state by the first power terminal or the second power terminal under control of the first clock signal terminal, the second clock signal terminal and the signal input terminal, so that the signal output terminal outputs a delay holding signal;
in a high-level signal outputting period, controlling, by the input sub-circuit, the first node to be in an off state according to the signals of the input signal terminal and the first clock signal terminal; and controlling, by the control sub-circuit, the second node to be in an on state by the first power terminal or the second power terminal under control of the first clock signal terminal, the second clock signal terminal and the signal input terminal, so that the signal output terminal outputs a high-level signal; and
in a low-level signal outputting period, controlling, by the input sub-circuit, the first node to be in an on state according to the signals of the input signal terminal and the first clock signal terminal; and controlling, by the control sub-circuit, the second node to be in an off state by the first power terminal or the second power terminal under control of the first clock signal terminal, the second clock signal terminal and the signal input terminal, so that the signal output terminal outputs a low-level signal.

8. A gate driving circuit, comprising a plurality of cascaded shifting registers according to claim 1 ; wherein
an input signal terminal of a first stage of shifting register is configured to be coupled to a frame start signal terminal; and
in every two adjacent shifting registers, an input signal terminal of a next stage of shifting register is configured to be coupled to an output terminal of a previous stage of shifting register.

9. A display device, comprising the gate driving circuit according to claim 8 .

10. The gate driving circuit according to claim 8 , wherein the input sub-circuit comprises a fifth transistor; and
a gate of the fifth transistor is coupled to the first clock signal terminal, a first electrode of the fifth transistor is coupled to the signal input terminal, and a second electrode of the fifth transistor is coupled to the first node.

11. The gate driving circuit according to claim 8 , wherein the control sub-circuit further comprises a sixth transistor; and
a gate of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the first power terminal, and a second electrode of the sixth transistor is coupled to the gate of the third transistor.

12. The gate driving circuit according to claim 8 , wherein the control sub-circuit further comprises a first capacitor; and
a first terminal of the first capacitor is coupled to the gate of the third transistor, and a

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Qing Haigang
• Hu Ming
• Qiu Haijun

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title