Memory device and computing method thereof

Patent metadata

Field	Value
Publication number	US-12423375-B2
Application number	US-202117502067-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Oct 15, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array, for processing a model computation, wherein the model computation has a plurality of input-values, a plurality of self-coefficients, a plurality of mutual-coefficients and a plurality of output-values, and the memory array comprises:
a plurality of first-word-lines and a plurality of second-word-lines;
a plurality of first-bit-lines and a plurality of second-bit-lines;
a plurality of common-source-lines; and
a plurality of memory cells, wherein the plurality of memory cells respectively receive the plurality of input-values through the plurality of first-word-lines, receive inverted logic values of the plurality of input-values through the plurality of second-word-lines, receive the plurality of input-values through the plurality of first-bit-lines, and receive the inverted logic values through the plurality of second-bit-lines and output the plurality of output-values through the plurality of common-source-lines,
wherein each of the plurality of memory cells performs a logic XNOR operation according to each of the plurality of input-values and each of the inverted logic values to obtain a first computation result, and multiplies the first computation result by one of the plurality of self-coefficients or one of the plurality of mutual-coefficients to obtain each of the plurality of output-values.

2. The memory device according to claim 1 , wherein each of the plurality of memory cells comprises:
a first transistor, coupled to an i-th first-word-line of the plurality of first-word-lines to be applied with a first-gate-voltage, coupled to a j-th first-bit-line of the plurality of first-bit-lines to be applied with a first-drain-voltage, and coupled to a j-th common-source-line of the plurality of common-source-lines to output a first-source-current; and
a second transistor, coupled to an i-th second-word-line of the plurality of second-word-lines to be applied with a second-gate-voltage, coupled to a j-th second-bit-line of the plurality of second-bit-lines to be applied with a second-drain-voltage, and coupled to the j-th common-source-line of the plurality of common-source-lines to output a second-source-current, wherein the second-source-current and the first-source-current are summed up to form a common-source-current,
wherein the first-gate-voltage corresponds to an i-th input-value of the plurality of input-values, the second-gate-voltage corresponds to an inverted logic value of the i-th input-value, the first-drain-voltage corresponds to a j-th input-value of the plurality of input-values, the second-drain-voltage corresponds to an inverted logic value of the j-th input-value, and the common-source-current corresponds to an output-value outputted by the j-th common-source-line.

3. The memory device according to claim 2 , wherein, if “i” is equal to “j”, an i-th input-value received by an i-th first-word-line is equal to a j-th input-value received by the j-th first-bit-line, an i-th input-value is an i-th spin state of a plurality of spin states.

4. The memory device according to claim 3 , wherein the first transistor has a first threshold voltage, the second transistor has a second threshold voltage, and if “i” is equal to “j”, the first threshold voltage and the second threshold voltage correspond to one of the plurality of self-coefficients.

5. The memory device according to claim 4 , wherein, if “i” is not equal to “j”, the first threshold voltage and the second threshold voltage correspond to one of the plurality of mutual-coefficients.

6. The memory device according to claim 2 , wherein if “i” is not equal to “one” and “i” is equal to (j+1), an i-th input-value received by an i-th first-word-line is equal to a j-th input-value receive by a j-th first-bit-line, and the i-th input-value is an i-th spin state of a plurality of spin states.

7. The memory device according to claim 6 , wherein the first transistor has a first threshold voltage, the second transistor has a second threshold voltage, and if “i” is equal to “one”, the first threshold voltage and the second threshold voltage correspond to one of the plurality of self-coefficients.

8. The memory device according to claim 7 , wherein, if “i” is not equal to “one” and “i” is not equal to (j+1), the first threshold voltage and the second threshold voltage correspond to one of the plurality of mutual-coefficients.

9. The memory device according to claim 2 , further comprising:
a plurality of sensing amplifiers, respectively coupled to the plurality of common-source-lines, wherein each of the plurality of sensing amplifiers sums up a plurality of output-values of a corresponding common-source-line to form a total-output-value.

10. The memory device according to claim 9 , further comprising:
an updating circuit, for comparing the total-output-value of each of the plurality of common-source-lines with a threshold value, and updating a j-th input-value received by a j-th first-bit-line if the total-output-value of a j-th common-source-line is greater than the threshold value.

11. A computing method of a memory device, comprising:
receiving a plurality of input-values of a model computation through a plurality of first-word-lines of a memory array;
receiving inverted logic values of the plurality of input-values through a plurality of second-word-lines of the memory array;
receiving the plurality of input-values through a plurality of first-bit-lines of the memory array;
receiving the inverted logic values through a plurality of second-bit-lines of the memory array;
performing a logic XNOR operation according to each of the plurality of input-values and each of the inverted logic values to obtain a first computation result;
multiplying the first computation result by one of a plurality of self-coefficients of the model computation or one of a plurality of mutual-coefficients of the model computation to obtain a plurality of output-values of the model computation; and
outputting the plurality of output-values respectively through a plurality of common-source-lines of the memory array.

12. The computing method according to claim 11 , wherein the memory array comprises a plurality of memory cells, each of the plurality of memory cells comprises a first transistor and a second transistor, and the computing method further includes:
applying a first-gate-voltage to the first transistor through an i-th first-word-line of the plurality of first-word-lines, wherein the first-gate-voltage corresponds to an i-th input-value of the plurality of input-values;
applying a first-drain-voltage to the first transistor through a j-th first-bit-line of the plurality of first-bit-lines, wherein the first-drain-voltage corresponds to a j-th input-value of the plurality of input-values;
outputting a first-source-current of the first transistor through a j-th common-source-line of the plurality of common-source-lines;
applying a second-gate-voltage to the second transistor through an i-th second-word-line of the plurality of second-word-lines, wherein the second-gate-voltage corresponds to an inverted logic value of the i-th input-value;
applying a second-drain-voltage to the second transistor through a j-th second-bit-line of the plurality of second-bit-lines, wherein the second-drain-voltage corresponds to an inverted logic value of the j-th input-value;
outputting a second-source-current of the second transistor through the j-th common-source-line of the plurality of common-source-lines; and
summing up the second-source-current and the first-source-current to form a common-source-current, wherein the common-source-current corresponds to an output-valu

Assignees

• Macronix Int Co Ltd

Inventors

• Wang Yun-Yuan
• Wei Ming-Liang
• Lee Ming-Hsiu
• Lu Cheng-Hsien

Classifications

• G06G7/32

  for solving of equations {or inequations; for matrices} · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0458

  comprising two or more independent floating gates which store independent data · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title