Memory controller for controlling memory dies and memory system including the memory controller

Patent metadata

Field	Value
Publication number	US-12423225-B2
Application number	US-202318391654-A
Country	US
Kind code	B2
Filing date	Dec 21, 2023
Priority date	Jul 7, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A memory system includes: a plurality of memory dies each including a plurality of memory blocks each including a plurality of pages, each of the memory dies being configured to store therein map data having a tree structure and a memory controller configured to organize super blocks each including memory blocks from the respective memory dies, configured to control an operation of copying data from a first memory block to a second memory block among the plurality of memory blocks and configured to update the map data according to the operation.

First claim

What is claimed is:

1. A memory system comprising:
a plurality of memory dies each including a plurality of memory blocks each including a plurality of pages, each of the memory dies being configured to store therein map data having a tree structure; and
a memory controller configured to organize super blocks each including memory blocks from the respective memory dies, configured to control an operation of accessing a target memory block among the plurality of memory blocks and configured to update the map data according to the operation,
wherein the map data includes root nodes respectively identifying the super blocks, die nodes respectively identifying the plurality of memory dies, and page nodes respectively identifying the plurality of pages, and
wherein the memory controller identifies, based on a target block address of the target memory block, a target root node among the root nodes, corresponding to a target super block including the target memory block.

2. The memory system of claim 1 , wherein the memory controller reads the target root node based on a super block table including addresses of the root nodes.

3. The memory system of claim 2 , wherein the memory controller identifies, based on the target block address, a target die node among the die nodes, corresponding to a target memory die including the target memory block.

4. The memory system of claim 3 , wherein the memory controller reads the target die node based on addresses of die nodes associated with the target root node.

5. The memory system of claim 4 , wherein the memory controller reads a target page node corresponding to a target page in which the data is stored among the plurality of pages included in the target memory block, based on addresses of page nodes associated with the target die nodes and an address of the target page, and acquires from the target page node a map entry representing a target logical address mapped to the address of the target page.

6. The memory system of claim 5 , wherein the memory controller maps the target logical address to an address of a second page in which the data is to be stored among the plurality of pages included in the second memory block.

7. The memory system of claim 4 , wherein, after the operation, the memory controller sets unmap information in each of the target die node and page nodes associated with the target die node or erases the target die node and the page nodes associated with the target die node.

8. A memory controller comprising:
a buffer memory configured to store map data having a tree structure, the map data being read from a plurality of memory dies each including a plurality of memory blocks each including a plurality of pages; and
a processor configured to organize super blocks each including two or more of the plurality of memory blocks from each of the memory dies, and configured to control, based on the map data, an operation on a memory block among the plurality of memory blocks,
wherein the map data includes root nodes respectively identifying the super blocks, die nodes respectively identifying the plurality of memory dies, block nodes respectively identifying the plurality of memory blocks, and page nodes respectively identifying the plurality of pages, and
wherein the processor reads, based on a block address corresponding to a selected memory block of the memory blocks, a root node and a die node respectively representing a selected super block of the super blocks and a selected memory die of the memory dies both including the selected memory block.

9. The memory controller of claim 8 , wherein the processor reads, based on the block address, a block node corresponding to the selected memory block among block nodes associated with the die node.

10. The memory controller of claim 9 , wherein the processor reads data stored in a first page among the plurality of pages included in the selected memory block, and acquires a logical address corresponding to the address of the first page from a first page node corresponding to the first page among page nodes associated with the block node, the first page node being identified based on an address of the first page.

11. The memory controller of claim 9 , wherein the processor stores, in the buffer memory, a page node including a map entry in which a logical address mapped to an address of a second page among the plurality of pages included in another memory block is mapped to an address of a first page among the plurality of pages included in the selected memory block, and stores, in the first page, data stored in the second page.

12. The memory controller of claim 10 , wherein the processor:
stores, in the plurality of memory dies, the map data stored in the buffer memory in response to sudden power off; and
reads, in response to power-on, the root nodes from the plurality of memory dies into the buffer memory based on a super block table including addresses of the root nodes.

13. An operating method of a controller, the operating method comprising:
updating map data of a tree structure including a hierarchy of:
root nodes representing respective super blocks,
intermediate nodes for a corresponding root node of the root nodes and representing respective memory dies related to a corresponding super block of the super blocks, and
leaf nodes for a corresponding intermediate node of the intermediate nodes and representing respective pages included in a corresponding memory die of the memory dies,
wherein the updating the map data includes:
identifying, based on a memory block address, a selected root node of the root nodes and a selected intermediate node of the intermediate nodes corresponding to the selected root node;
identifying, based on a page address, a selected leaf node of the leaf nodes corresponding to the selected intermediate node; and
updating an entry associated to the selected leaf node, the entry representing a mapping relationship between a logical address and the page address.

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/064

  Management of blocks · CPC title