Display panel, method of manufacturing the same and display device

Patent metadata

Field	Value
Publication number	US-12419166-B2
Application number	US-202418430616-A
Country	US
Kind code	B2
Filing date	Feb 1, 2024
Priority date	May 9, 2020
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

The present disclosure provides a display panel, a method of manufacturing the same, and a display device. The initialization signal line layer in the display panel includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas; the first auxiliary signal line layer includes a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area, at least part of the first auxiliary signal line pattern extends along the first direction, and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled.

First claim

What is claimed is:

1. A display panel, comprising: a substrate, an initialization signal line layer and a first auxiliary signal line layer sequentially stacked on the substrate along a direction away from the substrate; and a plurality of sub-pixel areas arranged in an array, wherein the plurality of sub-pixel areas form a plurality of rows of sub-pixel areas arranged in sequence along a second direction, each row of sub-pixel areas includes a plurality of sub-pixel areas arranged along a first direction, the first direction and the second direction intersect;
the initialization signal line layer includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas;
the first auxiliary signal line layer includes a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area, at least part of the first auxiliary signal line pattern extends along the first direction, and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled,
the display panel further includes a transistor structure, the initialization signal line pattern and an active layer in the transistor structure are arranged at a same layer;
wherein the display panel further comprises:
a power supply signal line layer located on a side of the initialization signal line layer away from the substrate, wherein the power supply signal line layer includes a power supply signal line pattern arranged in each of the plurality of sub-pixel areas, at least part of the power supply signal line pattern extends along the second direction;
a third auxiliary signal line layer located between the initialization signal line layer and the power supply signal line layer, wherein the third auxiliary signal line layer includes a third auxiliary signal line pattern located in each of the plurality of sub-pixel areas, at least part of the third auxiliary signal line pattern extends along the first direction; in the same sub-pixel area, there is a fourth overlapping area between an orthographic projection of the third auxiliary signal line pattern on the substrate and an orthographic projection of a power signal line pattern on the substrate, and the third auxiliary signal line pattern is coupled to the power signal line pattern in the fourth overlapping area; third auxiliary signal line patterns in a same row of sub-pixel areas along the first direction are sequentially coupled;
wherein the display panel further comprises:
a light-emitting control signal line layer, wherein the light-emitting control signal line layer includes a light-emitting control signal line pattern located in each of the plurality of sub-pixel areas, and at least part of the light-emitting control signal line pattern extends along the first direction;
a reset signal line layer, wherein the reset signal line layer includes a reset signal line pattern located in each of the plurality of sub-pixel areas, and the reset signal line pattern extends along the first direction;
in the same sub-pixel area, the orthographic projection of the third auxiliary signal line pattern on the substrate is located between the orthographic projection of the light-emitting control signal line pattern on the substrate and the orthographic projection of the reset signal line pattern on the substrate, the third auxiliary signal line pattern is formed in a wavy structure.

2. The display panel according to claim 1 , wherein the display panel further comprises:
a conductive connection portion layer located on a side of the first auxiliary signal line layer away from the substrate, wherein the conductive connection portion layer includes second conductive connection portions corresponding to the plurality of the sub-pixel areas in a one-to-one manner; in the same sub-pixel area, there is a first overlapping area between an orthographic projection of the second conductive connection portion on the substrate and an orthographic projection of the initialization signal line pattern on the substrate, and there is a second overlapping area between the orthographic projection of the second conductive connection portion on the substrate and the first auxiliary signal line pattern, the second conductive connection portion is coupled to the initialization signal line pattern in the first overlapping area, and the second conductive connection portion is coupled to the first auxiliary signal line pattern in the second overlapping area.

3. The display panel according to claim 2 , wherein the first auxiliary signal line pattern includes a first portion and a second portion coupled to each other, and the first portion extends along the first direction, the second portion protrudes from the first portion along a direction perpendicular to the first direction; an orthographic projection of the first portion on the substrate overlaps the orthographic projection of the initialization signal line pattern on the substrate overlap, and an orthographic projection of the second portion on the substrate does not overlap the orthographic projection of the initialization signal line pattern on the substrate;
in the same sub-pixel area, there is the second overlapping area between the orthographic projection of the second portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate.

4. The display panel according to claim 1 , wherein there is a third overlapping area between an orthographic projection of the first auxiliary signal line pattern on the substrate and the orthographic projection of the initialization signal line pattern on the substrate, the first auxiliary signal line pattern is directly coupled to the initialization signal line pattern through a via hole located in the third overlapping area.

5. The display panel according to claim 4 , wherein the first auxiliary signal line pattern includes a third portion and a fourth portion, the third portion extends along the first direction, in a direction perpendicular to the first direction, a width of the fourth portion is greater than a width of the third portion; there is the third overlapping area between an orthographic projection of the fourth portion on the substrate and the orthographic projection of the initialization signal line pattern on the substrate.

6. The display panel according to claim 1 , wherein the display panel further includes a power signal line layer and a data line layer that are sequentially stacked on the first auxiliary signal line layer along a direction away from the substrate;
the power signal line layer includes a power signal line pattern located in each of the plurality of sub-pixel areas, and at least part of the power signal line pattern extends along the second direction;
the data line layer includes a data line pattern located in each of the plurality of sub-pixel areas, and at least part of the data line pattern extends along the second direction;
in the same sub-pixel area, an orthographic projection of the power signal line pattern on the substrate overlaps an orthographic projection of the data line pattern on the substrate.

7. The display panel according to claim 1 , wherein the display panel further comprises a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate opposite to each other, the first electrode plate is located between the substrate and the second electrode plate, and the first electrode plate and a gate electrode of the transistor structure are arranged at a same layer and made of a same material; the first auxiliar

Assignees

• Boe Technology Group Co Ltd

Inventors

• Chen Yipeng
• Huangfu Lujiang
• Liu Libin

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/1201 Primary

  Manufacture or treatment · CPC title

• H10K59/351

  comprising more than three subpixels, e.g. red-green-blue-white [RGBW] · CPC title