Semiconductor device

Patent metadata

Field	Value
Publication number	US-12419067-B2
Application number	US-202117403666-A
Country	US
Kind code	B2
Filing date	Aug 16, 2021
Priority date	Feb 3, 2015
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of trenches with each trench of the plurality of trenches having a stripe-shape and a pair of linear sidewalls continuously provided from a surface of a semiconductor substrate to a curved interface in form of a curved bottom surface between the pair of linear sidewalls of each trench of the plurality of trenches in a depth direction, each trench of the plurality of trenches extending in parallel to each other in which a polysilicon electrode is provided through an insulating film;
a plurality of mesa regions between adjacent trenches of the plurality of trenches, the plurality of mesa regions constituted by a minute-pattern in a range with a width of 0.1 micro meters to 1.0 micro meter;
an interlayer insulating film covers a top surface of the plurality of mesa regions;
a plurality of contact holes in the interlayer insulating film between the adjacent trenches,
each contact hole of the plurality of contact holes corresponds to a mesa region of the plurality of mesa regions above the top surface of the mesa region between the adjacent trenches,
each contact hole of the plurality of contact holes penetrates the interlayer insulating film to the top surface of each mesa region of the plurality of mesa regions, and
each contact hole of the plurality of contact holes extends along the plurality of trenches in a longitudinal direction in a plan view;

a metal material buried in the plurality of contact holes;
a plurality of emitter regions of a first conductivity type periodically provided in the plurality of mesa regions along the longitudinal direction so as not to overlap the polysilicon electrode in the plan view;
a base region of a second conductivity type provided immediately below the plurality of emitter regions; and
a plurality of contact regions of the second conductivity type having a higher impurity concentration than the base region, provided in the longitudinal direction so as not overlap the polysilicon electrode in the plan view,
wherein
a length of a surface of an emitter region, among the plurality of emitter regions, in the longitudinal direction in the plan view is greater than a length of a surface of a contact region, among the plurality of contact regions, between two emitter regions among the plurality of emitter regions,
a length of an interface of a contact region, among the plurality of contact regions, with the base region in the longitudinal direction is greater than a length of an interface of the emitter region with the base region in the longitudinal direction, and
the metal material buried in a contact hole among the plurality of contact holes includes:
a barrier-metal film covering at least a part of an inner wall of the contact hole; and
tungsten plug including a tungsten film in contact with the barrier-metal film and provided in the contact hole, so that the tungsten plug is in contact with the mesa region constituted by the minute-pattern via the barrier-metal film, resulting in a contact area of the tungsten plug with the emitter region being larger than that with the contact region.

2. The semiconductor device according to claim 1 , wherein aspect ratio of a width of one of the plurality of contact holes in a second direction substantially perpendicular to the longitudinal direction in the plan view to a depth from a top surface of the interlayer insulating film to a bottom surface of the metal material is 0.8. to 1.5.

3. The semiconductor device according to claim 1 , wherein a portion of the barrier-metal film is selectively removed in one of the plurality of contact holes to form an edge.

4. The semiconductor device according to claim 1 , wherein the contact plug has a concave surface portion formed by recessing a surface of the contact plug.

5. The semiconductor device according to claim 4 , further comprising an emitter electrode in contact with the concave surface portion of the contact plug.

6. The semiconductor device according to claim 5 , wherein at least a part of a contact portion between the emitter electrode and the concave surface portion is provided in one of the plurality of contact holes.

7. The semiconductor device according to claim 1 , wherein the barrier-metal film includes at least any one of a titanium film and a titanium nitride film.

8. The semiconductor device according to claim 1 , wherein the tungsten plug results in the semiconductor device having a cross section in which a bottom surface of the tungsten plug is in contact with only the emitter region via the barrier-metal film and passes through the emitter region in a direction substantially perpendicular to the longitudinal direction in the plan view.

9. The semiconductor device according to claim 5 , wherein the emitter electrode includes an aluminum film or an aluminum alloy film including any one of an aluminum-silicon alloy, an aluminum-copper alloy, and an aluminum-copper-silicon alloy.

10. The semiconductor device according to claim 1 , wherein a trench of the plurality of trenches has a depth of 5 micro meters to 10 micro meters.

11. The semiconductor device according to claim 1 , wherein the insulating film provided inside each trench of the plurality of trenches has a substantially constant film thickness.

12. The semiconductor device according to claim 1 , wherein a width of a mesa region among the plurality of mesa regions is substantially constant in a depth direction.

13. The semiconductor device according to claim 1 , wherein the contact region has an impurity concentration of about 3×10 18 /cm 3 to 3×10 19 /cm 3 .

14. The semiconductor device according to claim 1 , wherein the emitter region or the contact region is exposed through a bottom of the contact hole.

15. The semiconductor device according to claim 1 , wherein a width of the emitter region or the contact region in a second direction substantially perpendicular to the longitudinal direction in the plan view is equal to a width of one of the plurality of mesa regions.

16. The semiconductor device according to claim 1 , wherein a bottom of the contact region is deeper than a bottom of the emitter region.

17. The semiconductor device according to claim 16 , wherein the plurality of contact regions are periodically provided in the longitudinal direction in the plan view.

18. The semiconductor device according to claim 17 , wherein two contact regions of the plurality of contact regions wrap around and sandwich a bottom of the emitter region.

19. The semiconductor device according to claim 1 , wherein a thickness of the insulating film at a portion contacting each emitter region of the plurality of emitter regions is substantially equal to or greater than a thickness at other portions of the insulating film.

20. The semiconductor device according to claim 1 , where a bottom of the contact hole is located substantially at a surface of an upper part of the mesa region.

21. The semiconductor device according to claim 1 , wherein the contact hole has angled sidewalls so that a top of the contact hole is wider than a bottom of the contact hole.

22. A semiconductor device comprising:
a plurality of trenches with each trench of the plurality of trenches having a stripe-shape and a pair of linear sidewalls continuously provided from a surface of a semiconductor substrate to a curved interface in form of a curved bottom surface between the pair of linear sidewalls of each trench of the plurality of trenches in a depth

Assignees

• Fuji Electric Co Ltd

Inventors

• Abe Hitoshi
• Miyata Hiroshi
• Takahashi Hidenori
• Noguchi Seiji
• Shimada Naoya

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title