Inter-symbol interference compensation for analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12418306-B2
Application number	US-202318218366-A
Country	US
Kind code	B2
Filing date	Jul 5, 2023
Priority date	Jul 5, 2023
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

First claim

What is claimed is:

1. A system, comprising:
a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal, wherein the digital signal is a digital approximation of the analog input signal;
a bitstream modifier configured to:
receive the digital signal from the sigma-delta ADC,
output a first signal at a first output terminal, wherein the first signal is based on the digital signal, and
output a first difference signal at a second output terminal, wherein the first difference signal includes a first difference value between a first value of the digital signal and a second value of the digital signal, wherein the second value is immediately prior to the first value in the digital signal; and

an error correction system, configured to:
receive the first signal from the first output terminal of the bitstream modifier,
receive the first difference signal from the second output terminal of the bitstream modifier,
use the first signal and the first difference signal to determine a correction value, and
modify the digital signal to generate a corrected digital signal by applying the correction value;

wherein the bitstream modifier is configured to:
determine a second difference value between the first value of the digital signal and the second value of the digital signal,
determine a first squared difference value of the second difference value, and
output the first squared difference value at a third output terminal of the bitstream modifier.

2. The system of claim 1 , wherein the error correction system is configured to receive the first squared difference value from the third output terminal of the bitstream modifier and use the first squared difference signal to determine the correction value.

3. The system of claim 2 , wherein the bitstream modifier is configured to:
determine a third difference value between the second value of the digital signal and a third value of the digital signal, wherein the third value is immediately prior to the second value in the digital signal,
determine a second squared value of the third difference value, and
output the second squared difference value of the third difference at a fourth output terminal as a second squared difference signal.

4. The system of claim 3 , wherein the error correction system is configured to receive the second squared difference value from the fourth output terminal of the bitstream modifier and use the second squared difference signal from the fourth output terminal to determine the correction value.

5. A system, comprising:
a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal, wherein the digital signal is a digital approximation of the analog input signal;
a bitstream modifier configured to:
receive the digital signal from the sigma-delta ADC,
output a first signal at a first output terminal, wherein the first signal is based on the digital signal, and
output a first difference signal at a second output terminal, wherein the first difference signal includes a first difference value between a first value of the digital signal and a second value of the digital signal, wherein the second value is immediately prior to the first value in the digital signal; and

an error correction system, configured to:
receive the first signal from the first output terminal of the bitstream modifier,
receive the first difference signal from the second output terminal of the bitstream modifier
use the first signal and the first difference signal to determine a correction value, and
modify the digital signal to generate a corrected digital signal by applying the correction value;

wherein the error correction system is configured to receive a parameter value from a sensor, wherein the output of the sigma-delta ADC varies as a function of a value of the parameter and the parameter includes at least one of a semiconductor manufacturing related process variation, a voltage, and a temperature.

6. The system of claim, 5 wherein the bitstream modifier is configured to:
determine a second difference value between the first value of the digital signal and the second value of the digital signal,
determine a first squared difference value of the second difference value, and
output the first squared difference value at a third output terminal of the bitstream modifier.

7. The system of claim 5 , wherein the error correction system includes a neural network that has been configured by a training phase to compensate for variations in the output of the sigma-delta ADC using the parameter.

8. A system, comprising:
a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal, wherein the digital signal is a digital approximation of the analog input signal;
a bitstream modifier, including:
an input terminal configured to receive the digital signal from the sigma-delta ADC,
a first signal path connected between the input terminal of the bitstream modifier and a first output terminal of the bitstream modifier to output a first signal at the first output terminal,
a first filter between the input terminal of the bitstream modifier and the first output terminal of the bitstream modifier,
a second signal path connected between the input terminal of the bitstream modifier and a second output terminal of the bitstream modifier, wherein the second signal path includes a first circuit configured to determine a first difference value between a first value of the digital signal and a second value of the digital signal, wherein the second value is immediately prior to the first value in the digital signal, and output the first difference value at the second output terminal as a first difference signal, and
a second filter between the first circuit of the second signal path and the second output terminal of the bitstream modifier; and

an error correction system, including:
a first input terminal connected to the first output terminal of the bitstream modifier,
a second input terminal connected to the second output terminal of the bitstream modifier, and
a neural network configured to:
use the first signal from the first output terminal and the first difference signal from the second output terminal to determine a correction value, and
modify the digital signal to generate a corrected digital signal by applying the correction value to compensate for inter-symbol interference in the digital signal.

9. The system of claim 8 , wherein the first filter is configured to attenuate signals having frequencies outside a first bandwidth and the second filter is configured to attenuate signals having frequencies outside a second bandwidth and wherein the first bandwidth is equal to the second bandwidth.

10. The system of claim 8 , wherein the bitstream modifier includes a third signal path connected between the input terminal of the bitstream modifier and a third output terminal of the bitstream modifier, wherein the third signal path includes:
a second circuit configured to determine a second difference value between the first value of the digital signal and the second value of the digital signal,
a third circuit configured to determine a first squared value of the second difference value, wherein the bitstream modifier is configured to output the first squared value of the second difference at the third output terminal as a first squared difference signal, and
a third filter connected between the third circuit and the third output terminal of the bitstream modifier, the third filter being configured to attenuate signals having frequencies outside a third bandwidth.

11.

Assignees

• Nxp Bv

Inventors

• Molendijk Maarten Jelmar
• Van Veldhoven Robert

Classifications

• H04L25/03012

  operating in the time domain (H04L25/03165, H04L25/03178 take precedence) · CPC title

• H03M3/376

  Prevention or reduction of switching transients, e.g. glitches · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/354 Primary

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title