First metal structure, layout, and method

Patent metadata

Field	Value
Publication number	US-12417980-B2
Application number	US-202217752737-A
Country	US
Kind code	B2
Filing date	May 24, 2022
Priority date	May 24, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

First claim

What is claimed is:

1. An integrated circuit (IC) structure comprising:
first and second active areas extending in a first direction in a semiconductor substrate;
first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas;
a first metal segment extending in the second direction in a first metal layer, wherein the first metal segment overlies each of the first and second active areas between the first and second gate structures;
second and third metal segments extending in the first direction in a second metal layer, wherein the second metal segment overlies each of the first active area and the first metal segment and is electrically connected to the first metal segment; and
a gate via structure extending from the third metal segment to one of the first or second gate structures,
wherein the first and second metal segments are electrically connected to the second active area, electrically isolated from a first portion of the first active area between the first and second gate structures, and electrically connected to a second portion of the first active area extending beyond the first and second gate structures.

2. The IC structure of claim 1 , wherein
the first metal segment is electrically connected to the second active area through a source/drain via structure in direct contact with the second active area.

3. The IC structure of claim 1 , wherein
the second metal segment is electrically connected to the second portion of the first active area through a first metal layer via structure, a fourth metal segment in the first metal layer, and a source/drain via structure in direct contact with the second portion of the first active area.

4. The IC structure of claim 1 , wherein
the first gate structure and the first active area are configured as a first transistor,
the second gate structure and the first active area are configured as a second transistor, and
the first portion of the first active area comprises a shared source/drain terminal of the first and second transistors.

5. The IC structure of claim 1 , further comprising:
a power rail positioned in a back side of the semiconductor substrate; and
a via structure configured to electrically connect the power rail to the first portion of the first active area.

6. The IC structure of claim 1 , wherein
the first metal segment is electrically connected to a portion of the second active area between the first and second gate structures.

7. The IC structure of claim 6 , further comprising:
a fourth metal segment extending in the first direction in the second metal layer, wherein the fourth metal segment overlies and is electrically isolated from each of the portion of the second active area and the first metal segment.

8. The IC structure of claim 1 , further comprising:
a third active area extending between the first and second active areas, wherein the first and second metal segments are electrically isolated from a third portion of the third active area between the first and second gate structures.

9. The IC structure of claim 1 , wherein the third metal segment overlies the first metal segment.

10. An integrated circuit (IC) device comprising:
a plurality of active areas extending in a first direction in a semiconductor substrate;
a plurality of gate structures extending in a second direction perpendicular to the first direction, wherein the plurality of gate structures overlies the plurality of active areas;
a first plurality of metal segments extending in the second direction in a first metal layer, wherein a first metal segment of the first plurality of metal segments overlies first and second active areas of the plurality of active areas;
a second plurality of metal segments extending in the first direction in a second metal layer, wherein a first metal segment of the second plurality of metal segments overlies each of the first metal segment of the first plurality of metal segments and the first active area of the plurality of active areas, and is electrically connected to the first metal segment of the first plurality of metal segments; and
a gate via structure extending from a second metal segment of the second plurality of metal segments to a second gate structure of the plurality of gate structures,
wherein the first metal segments of each of the first and second pluralities of metal segments are electrically connected to the second active area of the plurality of active areas, electrically isolated from a first portion of the first active area of the plurality of active areas adjacent to the second gate structure of the plurality of gate structures, and electrically connected to a second portion of the first active area of the plurality of active areas.

11. The IC device of claim 10 , wherein
the first metal segment of the first plurality of metal segments is electrically connected to the second active area of the plurality of active areas through a first source/drain (S/D) via structure in direct contact with the second active area of the plurality of active areas, and
the first metal segment of the second plurality of metal segments is electrically connected to the second portion of the first active area of the plurality of active areas through a first metal layer via structure, a second metal segment of the first plurality of metal segments, and a second S/D via structure in direct contact with the second portion of the first active area of the plurality of active areas.

12. The IC device of claim 11 , further comprising:
a plurality of power rails positioned in a back side of the semiconductor substrate; and
a plurality of back-side via structures configured to electrically connect the plurality of active areas to the plurality of power rails,
wherein the first portion of the first active area of the plurality of active areas comprises a shared S/D terminal of a transistor series coupled between first and second power rails of the plurality of power rails.

13. The IC device of claim 12 , wherein
the gate via structure is one of two gate via structures extending from the second plurality of metal segments to the plurality of gate structures, and
the plurality of active areas, the plurality of gate structures, the two gate via structures, the first and second pluralities of metal segments, the first and second S/D via structures, the plurality of power rails, and the plurality of back-side via structures are configured as one of a NAND gate or a NOR gate.

14. The IC device of claim 12 , wherein
the gate via structure is one of four gate via structures extending from the second plurality of metal segments to the plurality of gate structures, and
the plurality of active areas, the plurality of gate structures, the four gate via structures, the first and second pluralities of metal segments, the first and second S/D via structures, the plurality of power rails, and the plurality of back-side via structures are configured as one of an and-or-invert (AOI) logic device or an or-and-invert (OAI) logic device.

15. The IC device of claim 12 , wherein
the gate via structure is one gate via structure of a plurality of gate via structures extending from the second plurality of metal segments to the plurality of gate structures, and
the plurality of active areas, the plurality of gate structures, the plurality of gate via structures, the first and second pluralities of metal segments, the first and second S/D via structures, the plurality of power rails, and the plurality of ba

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chi-Yu
• Chen Chih-Liang
• Wu Chia-Tien
• Lai Chih-Yu
• Chiu Shang-Hsuan

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title