Metal grinding pretreatment in semiconductor device fabrication method

Patent metadata

Field	Value
Publication number	US-12417947-B2
Application number	US-202217813654-A
Country	US
Kind code	B2
Filing date	Jul 20, 2022
Priority date	Mar 25, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a dielectric layer and an initial metal interconnect structure, the initial metal interconnect structure penetrates the dielectric layer and covers a top surface of the dielectric layer; treating an exposed surface of the initial metal interconnect structure by using a first gas; cleaning the exposed surface of the initial metal interconnect structure by using a first liquid; and grinding to remove a partial structure of the initial metal interconnect structure, wherein a retained part of the initial metal interconnect structure forms a metal interconnect structure.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing an initial structure, wherein the initial structure comprises a dielectric layer and an initial metal interconnect structure, and the initial metal interconnect structure penetrates the dielectric layer and covers a top surface of the dielectric layer;
treating an exposed surface of the initial metal interconnect structure by using a first gas, wherein the first gas has a reducibility, and a metal oxide on the exposed surface of the initial metal interconnect structure is reduced;
cleaning the exposed surface of the initial metal interconnect structure by using a first liquid; and
grinding to remove a partial structure of the initial metal interconnect structure, wherein a retained part of the initial metal interconnect structure located in the dielectric layer forms a metal interconnect structure;
wherein the initial structure further comprises a metal pad located at a bottom of the initial metal interconnect structure, and the providing an initial structure comprises:
providing a first structure, wherein the first structure comprises a media layer, and the metal pad is formed in the media layer;
forming the dielectric layer, wherein the dielectric layer covers the media layer;
removing a part of the dielectric layer, and forming a first trench, wherein the first trench exposes a part of a top surface of the metal pad;
forming an initial barrier layer, wherein the initial barrier layer covers the part of the top surface of the metal pad exposed, a trench wall of the first trench, and a top surface of a remaining part of the dielectric layer;
depositing a first material through a first process, wherein the first material covers the initial barrier layer, and forming an initial seed layer; and
depositing the first material through a second process, wherein the first material is grown on the initial seed layer, fills an empty part of the first trench, and covers the top surface of the remaining part of the dielectric layer, and forming an initial metal layer, wherein the initial barrier layer, the initial seed layer, and the initial metal layer jointly form the initial metal interconnect structure;
wherein the grinding to remove a partial structure of the initial metal interconnect structure comprises:
grinding the exposed surface of the initial metal interconnect structure by using a first grinding paste, and removing a partial structure of a top surface of the initial metal layer, wherein the first grinding paste comprises first abrasive particles; and
grinding by using a second grinding paste to remove a part of the initial metal layer and a part of the initial seed layer on the top surface of the remaining part of the dielectric layer, and exposing a top surface of the initial barrier layer, wherein the second grinding paste comprises second abrasive particles,
wherein a particle size of the first abrasive particle is greater than a particle size of the second abrasive particle, and a pH value of the first grinding paste is greater than a pH value of the second grinding paste.

2. The method of manufacturing a semiconductor structure according to claim 1 , wherein the first gas comprises a carbon-containing gas and/or a hydrogen-containing gas.

3. The method of manufacturing a semiconductor structure according to claim 2 , wherein the first gas comprises at least one of CO or H 2 .

4. The method of manufacturing a semiconductor structure according to claim 1 , wherein the treating an exposed surface of the initial metal interconnect structure by using a first gas comprises:
continuously injecting the first gas to the exposed surface of the initial metal interconnect structure at a first flow rate for a first duration,
wherein the first flow rate is 3 sccm to 10 sccm, and the first duration is 15 s to 30 s.

5. The method of manufacturing a semiconductor structure according to claim 1 , wherein the cleaning the exposed surface of the initial metal interconnect structure by using a first liquid comprises:
continuously spraying the first liquid to the exposed surface of the initial metal interconnect structure for a second duration, wherein the second duration is 15 s to 30 s.

6. The method of manufacturing a semiconductor structure according to claim 5 , wherein the first liquid comprises a weakly acidic liquid.

7. The method manufacturing of a semiconductor structure according to claim 1 , wherein the depositing a first material through a first process comprises:
depositing the first material through a vapor deposition process in an inert gas atmosphere, wherein the first material covers the initial barrier layer, and forming the initial seed layer.

8. The method of manufacturing a semiconductor structure according to claim 1 , wherein the depositing the first material through a second process comprises:
depositing the first material through an electroplating process or a sputtering process.

9. The method of manufacturing a semiconductor structure according to claim 1 , wherein the first material comprises at least one of copper or aluminum.

10. The method of manufacturing a semiconductor structure according to claim 1 , wherein the pH value of the first grinding paste is 5.5 to 7, and the pH value of the second grinding paste is 3.5 to 6.5.

11. The method of manufacturing a semiconductor structure according to claim 1 , comprising:
grinding the initial barrier layer by using a third grinding paste, and exposing the top surface of the remaining part of the dielectric layer.

12. The method of manufacturing a semiconductor structure according to claim 11 , wherein the third grinding paste comprises third abrasive particles, and a pH value of the third grinding paste is greater than the pH value of the second grinding paste.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ma Ke

Classifications

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title