Multilayer electronic component

US12417882B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12417882-B2
Application numberUS-202318384796-A
CountryUS
Kind codeB2
Filing dateOct 27, 2023
Priority dateDec 27, 2022
Publication dateSep 16, 2025
Grant dateSep 16, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer electronic component includes a body including a first external electrode including a first base plating layer disposed on a third surface of the body and connected to the first internal electrode and a first electrode layer disposed on the first base plating layer, and a second external electrode including a second base plating layer disposed on a fourth surface of the body and connected to the second internal electrode and a second electrode layer disposed on the second base plating layer, wherein the first and second electrode layers include conductive metal and glass, and a 30 μm×5 μm region selected from a cross-section of the first base plating layer in the first and second directions includes three or more Ni grains having a grain size of 4 μm or greater.

First claim

Opening claim text (preview).

What is claimed is: 1. A multilayer electronic component comprising: a body including a dielectric layer and first and second internal electrodes alternately disposed in a first direction with the dielectric layer interposed therebetween and including first and second surfaces of the body facing in the first direction, third and fourth surfaces of the body connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces of the body connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first base plating layer disposed on the third surface and connected to the first internal electrode and a first electrode layer disposed on the first base plating layer; and a second external electrode including a second base plating layer disposed on the fourth surface and connected to the second internal electrode and a second electrode layer disposed on the second base plating layer, wherein the first and second electrode layers include a conductive metal and glass, and a 30 μm×5 μm region selected from a cross-section of the first base plating layer in the first and second directions includes Ni grains, wherein three or more of the Ni grains have a grain size of 4 μm or greater. 2. The multilayer electronic component of claim 1 , wherein the 30 μm×5 μm region includes two or more of the Ni grains having a grain size of 5 μm or greater. 3. The multilayer electronic component of claim 1 , wherein an average grain size of the Ni grains included in the 30 μm×5 μm region is 3 μm or greater. 4. The multilayer electronic component of claim 1 , wherein the 30 μm×5 μm region has a size of 30 μm in the first direction, and is a region within 5 μm from an interface between the first base plating layer and the first electrode layer in the second direction. 5. The multilayer electronic component of claim 1 , wherein an average size of the first base plating layer in the second direction is 5 μm or greater. 6. The multilayer electronic component of claim 1 , wherein the first base plating layer includes Pd in a region adjacent to the first internal electrode. 7. The multilayer electronic component of claim 1 , wherein the first internal electrode includes Pd in a region adjacent to the first base plating layer. 8. The multilayer electronic component of claim 1 , wherein, in the cross-sections of the first and second base plating layers in the first and second direction, an area ratio of the Ni grains is 90% or more with respect to a total area of the cross-sections of the first and second base plating layers. 9. The multilayer electronic component of claim 1 , wherein the first and second base plating layers include Ni plating layers. 10. The multilayer electronic component of claim 1 , wherein the first and second base plating layers are disposed between an extension line of the first surface and an extension line of the second surface, wherein each of the extension lines of the first and second surfaces each surface is a line extending based on a flat portion of the first and second surfaces. 11. The multilayer electronic component of claim 1 , wherein T 1 ′/T 1 is 0.8 or more and 1.1 or less, in which T 1 is a size of the first base plating layer in the second direction measured at a center of the body in the first direction, and T 1 ′ is a size of the first base plating layer in the second direction measured in an area at which an outermost first internal electrode disposed in the first direction and the first base plating layer are connected. 12. The multilayer electronic component of claim 1 , wherein the conductive metal included in the first and second electrode layers comprises Cu. 13. The multilayer electronic component of claim 1 , wherein the first and second electrode layers extend to and disposed on at least a portion of the first and second surfaces. 14. The multilayer electronic component of claim 1 , wherein the first and second electrode layers include a first layer including the conductive metal and glass and a second layer disposed on the first layer and including the conductive metal and a resin. 15. The multilayer electronic component of claim 1 , wherein the first external electrode further includes a first plating layer disposed on the first electrode layer, and the second external electrode further includes a second plating layer disposed on the second electrode layer. 16. The multilayer electronic component of claim 15 , wherein the first and second plating layers include an Ni plating layer, an average grain size of an Ni grain included in the Ni plating layers of the first and second plating layer is smaller than an average grain size of an Ni grain included in the first and second base plating layers. 17. A multilayer electronic component comprising: a body including a dielectric layer and first and second internal electrodes alternately disposed in a first direction with the dielectric layer interposed therebetween and including first and second surfaces of the body facing in the first direction, third and fourth surfaces of the body connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces of the body connected to the first to fourth surfaces and facing in a third direction; a first external electrode including: a first base plating layer disposed on the third surface and connected to the first internal electrode; a first electrode layer disposed on the first base plating layer; and a first plating layer disposed on the first electrode layer, a second external electrode including: a second base plating layer disposed on the fourth surface and connected to the second internal electrode; a second electrode layer disposed on the second base plating layer; and a second plating layer disposed on the second electrode layer, wherein an average grain size of an Ni grain included in the Ni plating layers of the first and second plating layer is smaller than an average grain size of an Ni grain included in the first and second base plating layers. 18. The multilayer electronic component of claim 17 , wherein the first and second electrode layers include a conductive metal and glass. 19. The multilayer electronic component of claim 17 , wherein a 30 μm×5 μm region selected from a cross-section of the first base plating layer in the first and second directions includes the Ni grains, wherein three or more of the Ni grains have a grain size of 4 μm or greater. 20. The multilayer electronic component of claim 17 , wherein the 30 μm×5 μm region includes two or more of the Ni grains having a grain size of 5 μm or greater. 21. The multilayer electronic component of claim 17 , wherein an average grain size of the Ni grains included in the 30 μm×5 μm region is 3 μm or greater.

Assignees

Inventors

Classifications

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • Selection of materials · CPC title

  • Form of non-self-supporting electrodes · CPC title

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

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What does patent US12417882B2 cover?
A multilayer electronic component includes a body including a first external electrode including a first base plating layer disposed on a third surface of the body and connected to the first internal electrode and a first electrode layer disposed on the first base plating layer, and a second external electrode including a second base plating layer disposed on a fourth surface of the body and co…
Who is the assignee on this patent?
Samsung Electro Mech
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 16 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).