Array substrate and display device

Patent metadata

Field	Value
Publication number	US-12417741-B2
Application number	US-202318843127-A
Country	US
Kind code	B2
Filing date	Oct 23, 2023
Priority date	Nov 4, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

An array substrate includes a substrate, pixel driving circuits and conductive patterns. In each pixel driving circuit, a first electrode region of a driving transistor, a second electrode region of a data writing transistor and a second electrode region of a first light-emitting control transistor are connected through a conductive connection pattern. The pixel driving circuits are configured as odd-numbered row circuit groups and even-numbered row circuit groups. The odd-numbered row circuit groups and the even-numbered row circuit groups each include pixel driving circuits. An overlapping area of orthographic projections, of the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an odd-numbered row circuit group is less than an overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an even-numbered row circuit group.

First claim

What is claimed is:

1. An array substrate, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate, wherein
each pixel driving circuit of the plurality of pixel driving circuits includes transistors, and the transistors include a driving transistor, a data writing transistor and a first light-emitting control transistor;
the array substrate further comprises: first electrode regions and second electrode region of the transistors; a first electrode region of the driving transistor, a second electrode region of the data writing transistor and a second electrode region of the first light-emitting control transistor are connected through a conductive connection pattern, and the conductive connection pattern is a continuous pattern;
the plurality of pixel driving circuits are configured as: odd-numbered row circuit groups and even-numbered row circuit groups; the odd-numbered row circuit groups and the even-numbered row circuit groups each include pixel driving circuits arranged in a first direction; the odd-numbered row circuit groups and the even-numbered row circuit groups are alternately arranged in a second direction; the first direction and the second direction intersect;
the array substrate further comprises conductive patterns; the conductive patterns include a pattern in the pixel driving circuit that is located in a different layer from the conductive connection pattern;
an overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an odd-numbered row circuit group is less than an overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an even-numbered row circuit group.

2. The array substrate according to claim 1 , wherein the transistors further include a compensation transistor;
the array substrate further comprises: a gate pattern of the compensation transistor and second scan signal lines; the gate pattern of the compensation transistor is electrically connected to a second scan signal line; a second electrode region of the compensation transistor is connected to a second electrode region of the driving transistor;
the plurality of pixel driving circuits are further configured as: a plurality of pixel group units sequentially arranged in the second direction; each pixel group unit of the plurality of pixel group units includes: an odd-numbered row circuit group and an even-numbered row circuit group arranged adjacent to the odd-numbered row circuit group; each pixel group unit shares one second scan signal line.

3. The array substrate according to claim 1 , further comprising: a first semiconductor layer disposed on the substrate, the conductive connection pattern being located in the first semiconductor layer.

4. The array substrate according to claim 1 , further comprising: a shielding layer located on the substrate, and a first semiconductor layer disposed on a side of the shielding layer away from the substrate;
the conductive pattern being located in the shielding layer.

5. The array substrate according to claim 3 , further comprising: a shielding layer located between on the substrate and the first semiconductor layer, a first gate conductive layer disposed on a side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on a side of the first gate conductive layer away from the substrate, wherein the pixel driving circuit further includes a capacitor and a compensation transistor;
the capacitor includes a first plate and a second plate; the first plate is located in the first gate conductive layer, and the second plate is located in the second gate conductive layer; the first plate is electrically connected to a first electrode region of the compensation transistor, and the second plate is electrically connected to a power supply signal line;
the conductive pattern includes: a first portion located in the shielding layer and a second portion electrically connected to the second plate.

6. The array substrate according to claim 3 , further comprising: a first gate conductive layer disposed on a side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on a side of the first gate conductive layer away from the substrate; the conductive pattern being located in the second gate conductive layer.

7. The array substrate according to claim 6 , wherein an area of an orthographic projection, on the substrate, of the conductive pattern in the odd-numbered row circuit group is equal to an area of an orthographic projection, on the substrate, of the conductive pattern in the even-numbered row circuit group;
in the even-numbered row circuit group, the conductive connection pattern is connected to a first extension pattern located in the first semiconductor layer, and the orthographic projection, on the substrate, of the conductive pattern covers an orthographic projection, on the substrate, of the first extension pattern.

8. The array substrate according to claim 3 , further comprising:
a second gate conductive layer disposed on a side of the first semiconductor layer away from the substrate; and
second scan signal lines, the second scan signal lines being located in the second gate conductive layer;
wherein a conductive pattern and a second scan signal line are of a one-piece structure.

9. The array substrate according to claim 3 , further comprising:
a first source-drain metal layer disposed on a side of the first semiconductor layer away from the substrate, wherein the first source-drain metal layer includes third extension patterns, and a third extension pattern is connected to the conductive connection pattern through a via hole; and
a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, the second source-drain metal layer including power supply signal lines;
wherein a conductive pattern and a power supply signal line are of a one-piece structure; an overlapping area of orthographic projections, on the substrate, of a third extension pattern and the conductive pattern in the odd-numbered row circuit group is less than an overlapping area of orthographic projections, on the substrate, of a third extension pattern and the conductive pattern in the even-numbered row circuit group.

10. The array substrate according to claim 9 , wherein in the odd-numbered row circuit group, an orthographic projection of a power supply signal line on the substrate does not overlap with an orthographic projection of the third extension pattern on the substrate.

11. The array substrate according to claim 9 , wherein an orthographic projection of the third extension pattern on the substrate overlaps with an orthographic projection of the conductive connection pattern on the substrate.

12. The array substrate according to claim 1 , wherein
the transistors further include: a first reset transistor, a compensation transistor, a second light-emitting control transistor and a second reset transistor;
the array substrate further comprises: first initial signal lines, second initial signal lines, data signal lines and power supply signal lines;
a first electrode region of the first reset transistor is electrically connected to a first initial signal line, a second electrode region of the first reset transistor is electrically connected to a first electrode region of the compensation transistor, and a second electrode region of the compensation transistor is electrically connected to a s

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Qing Haigang
• Mou liangfeng
• Hu Ming
• Qiu Haijun

Classifications

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title