Display panel and display device

Patent metadata

Field	Value
Publication number	US-12417733-B2
Application number	US-202418735093-A
Country	US
Kind code	B2
Filing date	Jun 5, 2024
Priority date	May 6, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

First claim

What is claimed is:

1. A display panel, comprising a display area;
wherein the display panel further comprises:
a light-emitting element, wherein the light-emitting element is located in the display area;
a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;
a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and
N pixel circuit rows and N light-emitting element rows, wherein at least one of the N pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the N pixel circuit rows and the N light-emitting element rows are arranged along a second direction, the first direction and the second direction intersect;
wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded;
a shift register circuit of the plurality of stages of shift register circuits is disposed between the j-th pixel circuit row of the N pixel circuit rows and the (j+1)-th pixel circuit row of the N pixel circuit rows, wherein j≥1, j<N and j is an integer;
wherein at least one of the following is satisfied:
no shift register circuit is disposed between an N-th pixel circuit row of the N pixel circuit rows and an (N−1)-th pixel circuit row of the N pixel circuit rows and no shift register circuit is disposed between a first pixel circuit row of the N pixel circuit rows and a second pixel circuit row of the N pixel circuit rows; or
no shift register circuit is disposed between an N-th light-emitting element row of the N light-emitting element rows and an (N−1)-th light-emitting element row of the N light-emitting element rows and no shift register circuit is disposed between a first light-emitting element row of the N light-emitting element rows and a second light-emitting element row of the N light-emitting element rows.

2. The display panel of claim 1 , wherein
no shift register circuit is disposed between the i-th pixel circuit row of the N pixel circuit rows and the (i+1)-th pixel circuit row of the N pixel circuit rows, wherein i≥1, i<N and i is an integer.

3. A display panel, comprising a display area;
wherein the display panel further comprises:
a light-emitting element, wherein the light-emitting element is located in the display area;
a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;
light-emitting element rows;
a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and
pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect;
wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded;
the display panel comprises a j-th pixel circuit row and a (j+1)-th pixel circuit row, and a shift register circuit of the plurality of stages of shift register circuits is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row, wherein j≥1 and j is an integer;
wherein at least one of the light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction, and the light-emitting element rows are arranged along the second direction;
the j-th pixel circuit row and the (j+1)-th pixel circuit row are located between a j-th light-emitting element row and (j+1)-th light-emitting element row.

4. The display panel of claim 3 , wherein
the j-th pixel circuit row is configured to drive the j-th light-emitting element row, and the j-th pixel circuit row is configured to drive the j-th light-emitting element row.

5. The display panel of claim 1 , wherein
at least one of the N light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction;
the j-th pixel circuit row is disposed on a side of the j-th light-emitting element row away from the (j+1)-th light-emitting element row, and the (j+1)-th pixel circuit row is disposed on a side of the (j+1)-th light-emitting element row facing the j-th light-emitting element row; or
the j-th pixel circuit row is disposed on a side of the j-th light-emitting element row facing the (j+1)-th light-emitting element row, and the (j+1)-th pixel circuit row is disposed on a side of the (j+1)-th light-emitting element row away from the j-th light-emitting element row.

6. The display panel of claim 5 , wherein
the j-th pixel circuit row is configured to drive the j-th light-emitting element row, and the (j+1)-th pixel circuit row is configured to drive the (j+1)-th light-emitting element row.

7. The display panel of claim 2 , wherein
the j-th pixel circuit row and the (j+1)-th pixel circuit row are located in an area of the display area, and the i-th pixel circuit row and the (i+1)-th pixel circuit row are located in another area of the display area.

8. The display panel of claim 2 , wherein
the (N−1)-th pixel circuit row and the N-th pixel circuit row are located at an edge area of the display area.

9. The display panel of claim 8 , wherein
at least one of the N light-emitting element rows comprises a plurality of light-emitting elements arranged along the first direction;
along the second direction, the N-th light-emitting element row is located on a side of the N-th pixel circuit row facing an edge area of the display area; and
the N-th pixel circuit row is configured to drive the N-th light-emitting element row.

10. The display panel of claim 2 , wherein
the driver circuit comprises a scan driver circuit and a light-emitting control driver circuit;
wherein, the scan driver circuit is configured to provide a scan signal for the pixel circuit, and the scan driver circuit comprises a plurality of stages of scan shift register circuits cascaded; and
the light-emitting control driver circuit is configured to provide a light-emitting control signal to the pixel circuit, and the light-emitting control driver circuit comprises a plurality of stages of light-emitting control shift register circuits cascaded.

11. The display panel of claim 10 , wherein
at least one scan shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row; and/or,
at least one light-emitting control shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row.

12. The display panel of claim 10 , wherein
at least one scan shift register circuit is disposed between the j-th pixel circuit row and the (j+1)-th pixel circuit row;
the scan shift register circuit comprises a first latch module, a logic module and a first buffer module, and the first latch module, the logic module and the first buffer module are arranged along the first direction.

13. The display panel of claim 10 , wherein
at least one of the j-th pixel circuit row or the (j+1)-th pixel circuit row comprises a plurality of pixel circuit groups, and a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits;
along the first direction, a width of the scan shift register circuit is greater than a width of at least two pixel circuit groups.

14. The display panel of claim 10 , wherein
at least one light-emitting control shift register circuit i

Assignees

• Hubei Yangtze Ind Innovation Center Of Advanced Display Co Ltd

Inventors

• Dai Wenjun
• Xing Liang
• Wu Tianyi

Classifications

• G02F1/136204

  Arrangements to prevent high voltage or static electricity failures · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title