Fault tolerant Hastings-Haah codes in the presence of dead qubits

Patent metadata

Field	Value
Publication number	US-12417400-B2
Application number	US-202318332004-A
Country	US
Kind code	B2
Filing date	Jun 9, 2023
Priority date	Jun 9, 2023
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Aspects of the disclosure include removing a faulty qubit in a quantum circuit. The faulty qubit is determined to be in the quantum circuit, the faulty qubit being associated with a plaquette having other qubits, where adjacent plaquettes are neighboring the plaquette. A route is determined to isolate the plaquette from the adjacent plaquettes. Measurements are caused to be performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

First claim

What is claimed is:

1. A method for removing a faulty qubit in a quantum circuit, the method comprising:
determining the faulty qubit in the quantum circuit, the faulty qubit being associated with a plaquette having other qubits, wherein adjacent plaquettes are neighboring the plaquette;
determining a route to isolate the plaquette from the adjacent plaquettes; and
causing measurements to be performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

2. The method of claim 1 , further comprising removing the faulty qubit and the other qubits of the plaquette from the route such that the measurements exclude the plaquette.

3. The method of claim 1 , wherein the route is structured to remove edges of the adjacent plaquettes from coupling to the plaquette having the faulty qubit in order to isolate the plaquette.

4. The method of claim 1 , wherein the measurements are performed on the quantum circuit such that edges of the adjacent plaquettes are isolated from the plaquette having the faulty qubit in order to isolate the plaquette.

5. The method of claim 1 , wherein the route is structured to reconnect edges of the adjacent plaquettes without connecting to the plaquette.

6. The method of claim 1 , wherein Hastings-Haah code is implemented to perform the measurements.

7. The method of claim 1 , wherein the plaquette and the adjacent plaquettes are formed in a 4.8.8 lattice.

8. The method of claim 1 , further comprising receiving measurement outcomes from the quantum circuit in response to causing the measurements performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

9. A system having a memory, computer readable instructions, and a processor for executing the computer readable instructions, the computer readable instructions controlling the processor to perform operations comprising:
determining a faulty qubit in a quantum circuit, the faulty qubit being associated with a plaquette having other qubits, wherein adjacent plaquettes are neighboring the plaquette;
determining a route to isolate the plaquette from the adjacent plaquettes; and
causing measurements to be performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

10. The system of claim 9 , wherein the processor is controlled to perform the operations further comprising removing the faulty qubit and the other qubits of the plaquette from the route such that the measurements exclude the plaquette.

11. The system of claim 9 , wherein the route is structured to remove edges of the adjacent plaquettes from coupling to the plaquette having the faulty qubit in order to isolate the plaquette.

12. The system of claim 9 , wherein the measurements are performed on the quantum circuit such that edges of the adjacent plaquettes are isolated from the plaquette having the faulty qubit in order to isolate the plaquette.

13. The system of claim 9 , wherein the route is structured to reconnect edges of the adjacent plaquettes without connecting to the plaquette.

14. The system of claim 9 , wherein Hastings-Haah code is implemented to perform the measurements.

15. The system of claim 9 , wherein the plaquette and the adjacent plaquettes are formed in a 4.8.8 lattice.

16. The system of claim 9 , wherein the processor is controlled to perform the operations further comprising receiving measurement outcomes from the quantum circuit in response to causing the measurements performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

17. A system comprising:
a quantum circuit;
a computer coupled to the quantum circuit and comprising a processor controlled to perform operations comprising:
determining a faulty qubit in the quantum circuit, the faulty qubit being associated with a plaquette having other qubits, wherein adjacent plaquettes are neighboring the plaquette;
determining a route to isolate the plaquette from the adjacent plaquettes; and
causing measurements to be performed on the quantum circuit for the route that isolates the plaquette having the faulty qubit and the other qubits.

18. The system of claim 17 , wherein the processor is controlled to perform the operations further comprising removing the faulty qubit and the other qubits of the plaquette from the route such that the measurements exclude the plaquette.

19. The system of claim 17 , wherein the route is structured to remove edges of the adjacent plaquettes from coupling to the plaquette having the faulty qubit in order to isolate the plaquette.

20. The system of claim 17 , wherein the measurements are performed on the quantum circuit such that edges of the adjacent plaquettes are isolated from the plaquette having the faulty qubit in order to isolate the plaquette.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Hastings Matthew Benjamin
• Bonderson Parsa
• Wang Zhenghan
• Haah Jeongwan
• Aasen David Alexander

Classifications

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• G06N10/70 Primary

  Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title